IP Library Granted Patent US 9,960,117
Granted Patent B2
US 9,960,117 · App. 14/960,483 · Granted May 1, 2018

Air gap semiconductor structure with selective cap bilayer

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 9,960,117
App. No.
14/960,483
Granted
May 1, 2018
Kind
B2
Abstract

A semiconductor substrate including one or more conductors is provided. A first layer and a second layer are deposited on the top surface of the conductors. A dielectric cap layer is formed over the semiconductor substrate and air gaps are etched into the dielectric layer. The result is a bilayer cap air gap structure with effective electrical performance.

Claims (38)

1. A semiconductor structure comprising:

a dielectric layer present on a semiconductor substrate;

one or more conductors within the dielectric layer, wherein the one or more conductors have a top surface and a lower surface, wherein the top surface has a height equal to the dielectric layer, and wherein the bottom surface has a barrier layer;

a bilayer cap present on the one or more conductors, wherein the bilayer cap comprises a first layer and a second layer, wherein the second layer is a protective layer containing carbon (C) based structures and is self-aligned to the top surface of the one or more conductors, and wherein the first layer is an adhesive layer, which promotes electromigration, comprising: one or more metals, and is between 1 nanometer (nm) to 10 nanometers (nm) thick;

a plurality of air gaps, wherein the plurality of air gaps are etched into the dielectric layer to a depth between 2 nm to 50 nm, below the top surface of the one or more conductors;

a modified layer on top of the dielectric layer within the plurality of air gaps, wherein the modified layer forms in response to removal of the carbon (C) based structures by plasma treatment; and

a dielectric cap layer, wherein the dielectric cap layer is a sacrificial protective layer.

2. The semiconductor structure of claim 1 , wherein the first layer comprises the adhesive layer, and is configured to be in adhesive contact with the one or more conductors.

3. The semiconductor structure of claim 1 , wherein the second layer comprises the protective layer, and is configured to be in adhesive contact with the first layer.

4. The semiconductor structure of claim 1 , wherein the first layer comprises one or more metals including: cobalt (Co), manganese (Mn), tantalum (Ta), ruthenium (Ru), aluminum (Al), nickel (Ni), tungsten (W), platinum (Pt), palladium (Pd), and rhenium (Re).

5. The semiconductor structure of claim 1 , wherein the first layer comprises an electroless metal capping layer, wherein the electroless metal capping layer comprises one or more of: NiWP and a selective chemical vapor deposition (CVD) Ru cap.

6. The semiconductor structure of claim 1 , wherein the second layer comprises an additional non-metal containing compound, wherein the non-metal containing compound includes: silicon (Si), nitrogen (N), and hydrogen (H).

7. The semiconductor structure of claim 6 , wherein the metal compound of the second layer comprises one or more of: a metal containing alloy including MC x , MN y , MC x N y , MSi x C y , MSi x N y , and MSi x N y C z , wherein M comprises one or more metals including: cobalt (Co), manganese (Mn), tantalum (Ta), ruthenium (Ru), aluminum (Al), nickel (Ni), tungsten (W), platinum (Pt), palladium (Pd), and rhenium (Re).

8. The semiconductor structure of claim 1 , wherein the one or more conductors selected from the group consisting of copper (Cu), aluminum (Al), and tungsten (W).

9. The semiconductor structure of claim 1 , wherein the first layer has a thickness of 4 nm.

10. The semiconductor structure of claim 1 , wherein the second layer comprises at least one of: a metal containing alloy including CoCH, CoSiNCH and CoSi x .

11. A semiconductor structure comprising:

a dielectric layer present on a semiconductor substrate;

one or more copper (Cu) conductors within the dielectric layer, wherein the one or more Cu conductors have a top surface and a bottom surface, wherein the top surface has a height equal to the dielectric layer, and wherein the bottom surface has a barrier layer;

a bilayer cap present on the one or more Cu conductors, wherein the bilayer cap comprises a repeated plurality of a first layer deposited on the top surface of the one or more Cu conductors and a second layer deposited on the first layer, wherein the first layer is an adhesive, which promotes electromigration, comprising: one or more metals, and is between 1 nm to 10 nm thick, and wherein the second layer contains carbon (C) based structures and is self-aligned to the top surface of the one or more Cu conductors of the first layer;

a plurality of air gaps, wherein the plurality of air gaps are etched to a depth between 2 nm to 50 nm, below the top surface of the one or more Cu conductors within the dielectric layer;

a surface modification of the first layer, wherein the surface modification of first layer modifies density;

a modified layer on top of the dielectric layer within the plurality of air gaps, wherein the modified layer forms in response to removal of the carbon (C) based structures by plasma treatment;

a dielectric cap layer, wherein the dielectric cap layer is a sacrificial protective layer; and

a deposited non-conformal cap layer and a deposited conformal cap layer, wherein the deposited non-conformal cap layer and the deposited conformal cap are above the bilayer cap.

12. The semiconductor structure of claim 11 , wherein the etched plurality of air gaps correspond to the bottom surface of the one or more Cu conductors.

13. The semiconductor structure of claim 11 , wherein the first layer has a thickness of 4 nm.

14. The semiconductor structure of claim 11 , wherein the second layer comprises at least one of: a metal containing alloy including CoCH, CoSiNCH and CoSi x .

15. A semiconductor structure comprising:

a dielectric layer present on a semiconductor substrate;

one or more conductors within the dielectric layer, wherein the one or more conductors have a top surface and a bottom surface, wherein the top surface has a height equal to the dielectric layer, and wherein the bottom surface has a barrier layer;

a bilayer cap present on the one or more conductors, wherein the bilayer cap comprises a first layer and a second layer, wherein the first layer is an adhesive, between 1 nm to 10 nm thick which promotes electromigration, comprising an electroless metal capping layer, wherein the electroless metal capping layer comprises one or more of: CoWP, CoWB, and NiWP and a selective CVD Ru cap and the second layer is a chemical modification of the first layer, wherein the second layer contains carbon (C) based structures;

a plurality of air gaps, wherein the plurality of air gaps are etched to a depth corresponding to a bottom surface of the one or more conductors within the dielectric layer;

a modified layer on top of the dielectric layer within the plurality of air gaps, wherein the modified layer forms in response to removal of the carbon (C) based structures by plasma treatment; and

a dielectric cap layer, wherein the dielectric cap layer is a sacrificial protective layer.

16. The semiconductor structure of claim 15 , wherein the dielectric cap layer covers a region of the semiconductor substrate blocked from selection for formation of the plurality of air gaps in response to modifying the dielectric cap layer.

17. The semiconductor structure of claim 15 , wherein a percentage of content of the first layer is equal to a starting content percentage of the first layer.

18. The semiconductor structure of claim 15 , wherein the first layer has a thickness of 4 nm.

Assignments (5)
CHANGE OF NAME Recorded Nov 21, 2025
From: TESSERA, INC.
To: TESSERA LLC
Reel/Frame 073658/0462 →
CHANGE OF NAME Recorded Nov 21, 2025
From: TESSERA LLC
To: ADEIA SEMICONDUCTOR SOLUTIONS LLC
Reel/Frame 073658/0849 →
SECURITY INTEREST Recorded Jun 1, 2020
From: ROVI SOLUTIONS CORPORATION; ROVI TECHNOLOGIES CORPORATION; ROVI GUIDES, INC.; TIVO SOLUTIONS INC.; VEVEO, INC.; INVENSAS CORPORATION; INVENSAS BONDING TECHNOLOGIES, INC.; TESSERA, INC.; TESSERA ADVANCED TECHNOLOGIES, INC.; DTS, INC.; PHORUS, INC.; IBIQUITY DIGITAL CORPORATION
To: BANK OF AMERICA, N.A.
Reel/Frame 053468/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 6, 2020
From: INTERNATIONAL BUSINESS MACHINES CORPORATION
To: TESSERA, INC.
Reel/Frame 051489/0557 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 7, 2015
From: GATES, STEPHEN M.; HUANG, ELBERT E.; KIOUSSIS, DIMITRI R.; PENNY, CHRISTOPHER J.; PRIYADARSHINI, DEEPIKA
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 037220/0771 →