Lowering parasitic capacitance of replacement metal gate processes
View Patent ↗The present disclosure provides a method of forming a gate structure of a semiconductor device with reduced gate-contact parasitic capacitance. In a replacement gate scheme, a high-k gate dielectric layer is deposited on a bottom surface and sidewalls of a gate cavity. A metal cap layer and a sacrificial cap layer are deposited sequentially over the high-k gate dielectric layer to form a material stack. After ion implantation in vertical portions of the sacrificial cap layer, at least part of the vertical portions of the material stack is removed. The subsequent removal of a remaining portion of the sacrificial cap layer provides a gate component structure. The vertical portions of the gate component structure do not extend to a top of the gate cavity, thereby significantly reducing gate-contact parasitic capacitance.
1. A method of forming a semiconductor structure comprising:
forming a gate cavity laterally surrounded by a planarization dielectric material layer on a semiconductor substrate, wherein a top surface of said semiconductor substrate is exposed at a bottom of said gate cavity;
forming a U-shaped high-k gate dielectric layer having a dielectric constant greater than 3.9, a U-shaped metal cap layer and a sacrificial cap layer in said gate cavity;
implanting ions into vertical portions of said U-shaped sacrificial cap layer to damage at least part of said vertical portions of said U-shaped sacrificial cap layer;
removing said damaged portions of said U-shaped sacrificial cap layer to expose portions of said U-shaped metal cap layer located directly beneath said damaged portions of said U-shaped sacrificial cap layer;
removing said exposed portions of said U-shaped metal cap layer to expose portions of said U-shaped high-k gate dielectric layer located directly beneath said exposed portions of said U-shaped metal cap layer;
removing said exposed portions of said U-shaped high-k gate dielectric layer; and
removing a remaining portion of said sacrificial cap layer.
2. The method of claim 1 , wherein an incident angle of said implanting is controlled so as to leave a horizontal portion of said sacrificial cap layer intact.
3. The method of claim 2 , wherein said implanting utilizes ions selected from the group consisting of oxygen, argon, helium, neon, and xenon.
4. The method of claim 3 , wherein said implanting uses a dosage ranging from 1×10 16 atoms/cm 2 to 5×10 17 atoms/cm 2 with an energy from 1 keV to 30 keV.
5. The method of claim 1 , wherein said U-shaped metal cap layer comprises titanium nitride (TiN), titanium silicon nitride (TiSiN), tantalum nitride (TaN), tantalum silicon nitride (TaSiN), titanium tantalum nitride (TiTaN), tantalum ruthenium (TaRuN), tungsten nitride (WN), tungsten silicon nitride (WSiN), or combinations thereof.
6. The method of claim 1 , wherein said U-shaped sacrificial cap layer comprises a semiconductor material or a dielectric material.
7. The method of claim 6 , wherein said U-shaped sacrificial cap layer comprises amorphous silicon or silicon germanium (SiGe).
8. The method of claim 6 , wherein said U-shaped sacrificial cap layer comprises silicon oxide (SiO 2 ) or silicon nitride (SiN).
9. The method of claim 1 , wherein a dielectric material of said high-k gate dielectric layer comprises hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, zirconium silicon oxynitride, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobate, or combinations thereof.
10. The method of claim 1 , further comprising forming a gate electrode to fill a recess region of said gate cavity after removing said remaining portion of said U-shaped sacrificial cap layer.
11. The method of claim 10 , wherein said gate electrode comprises a conductive metal portion made of a conductive metal selected from the group consisting of Al, W, Cu, Pt, Ag, Au, Ru, Ir, Rh, Re, alloys thereof, and silicides thereof.
12. The method of claim 10 , wherein said gate electrode comprises a work function metal portion and a conductive metal portion.
13. The method of claim 12 , wherein said work function metal portion comprises titanium nitride (TiN), tantalum nitride (TaN), titanium silicon nitride (TiSiN), tantalum silicon nitride (TaSiN), titanium carbide (TiC), tantalum carbide (TaC, Ta 2 C), tungsten nitride (WN), and combinations thereof, and wherein, the conductive metal portion comprises W, Cu, Pt, Ag, Au, Ru, Ir, Rh, Re, alloys thereof, or silicides thereof.
14. The method of claim 1 , further comprising:
forming a disposable gate structure on said semiconductor substrate;
forming and planarizing a planarization dielectric material layer on said semiconductor substrate, wherein a top surface of said planarization dielectric material layer is coplanar with a top surface of said disposable gate structure;
recessing said disposable gate structure to form said gate cavity over said semiconductor substrate prior to forming said U-shaped high-k gate dielectric layer.