Semiconductor device with different fin pitches
View Patent ↗A method for forming a semiconductor device includes forming a first fin and a second fin on a substrate, the first fin arranged in parallel with the second fin, the first fin arranged a first distance from the second fin, the first fin and the second fin extending from a first source/drain region through a channel region and into a second source/drain region on the substrate. The method further includes forming a third fin on the substrate, the third fin arranged in parallel with the first fin and between the first fin and the second fin, the third fin arranged a second distance from the first fin, the second distance is less than the first distance, the third fin having two distal ends arranged in the first source/drain region. A gate stack is formed over the first fin and the second fin.
1. A method for forming a semiconductor device, the method comprising:
forming a mandrel on a substrate;
forming sacrificial sidewall spacers along sidewalls of the mandrel;
removing the mandrel;
removing portions of the substrate to form an arrangement of fins on the substrate, the arrangement of fins including:
a first fin arranged substantially in parallel with a second fin in a source/drain region, the first fin arranged a first distance from the second fin; and
a third fin arranged substantially in parallel with a fourth fin in a channel region, the third fin arranged a second distance from the fourth fin, the second distance is greater than the first distance;
removing the sacrificial sidewall spacers; and
forming a gate stack over the channel region.
2. The method of claim 1 , further comprising forming spacers adjacent to the gate stack.
3. The method of claim 1 , wherein the first fin, the second fin, the third fin, and the fourth fin are formed from a semiconductor material.
4. The method of claim 1 , wherein the first fin contacts the third fin.
5. The method of claim 1 , wherein the second fin contacts the fourth fin.
6. The method of claim 1 , wherein the arrangement of fins further includes a fifth fin arranged substantially in parallel with the second fin in the source/drain region, the fifth fin contacting the third fin.
7. The method of claim 1 , wherein the arrangement of fins further includes a sixth fin arranged substantially in parallel with the second fin in the source/drain region, the sixth fin contacting the fourth fin.
8. The method of claim 1 , wherein the mandrel includes an amorphous carbon material.
9. The method of claim 1 , wherein the first fin comprises silicon.
10. The method of claim 1 , wherein the first fin comprises silicon germanium.
11. The method of claim 1 , wherein the removing portions of the substrate to form the arrangement of fins is performed using an anisotropic etching process.
12. The method of claim 2 , wherein the spacers include a nitride material.
13. A semiconductor device comprising:
a first semiconductor fin arranged in parallel with a second semiconductor fin in a first source/drain region on a substrate, the first semiconductor fin arranged a first distance from the second semiconductor fin;
a third semiconductor fin arranged in parallel with a fourth semiconductor fin in a channel region on the substrate, the third semiconductor fin arranged a second distance from the fourth semiconductor fin, the second distance greater than the first distance, the first semiconductor fin contacting the third semiconductor fin and the second semiconductor fin contacting the fourth semiconductor fin; and
a gate stack arranged over the channel region of the third semiconductor fin and the fourth semiconductor fin.
14. The device of claim 13 , further comprising a spacer arranged along sidewalls of the gate stack, the spacer arranged over a portion of the third semiconductor fin and the fourth semiconductor fin.
15. The device of claim 13 , wherein the first semiconductor fin comprises silicon.
16. The device of claim 13 , wherein the first semiconductor fin comprises silicon germanium.
17. The device of claim 13 , wherein the first semiconductor fin is arranged on a substrate.
18. The device of claim 13 , wherein the gate stack includes a gate metal material.
19. The device of claim 13 , further comprising a spacer arranged along sidewalls of the gate stack, the spacer arranged over a portion of the first semiconductor fin and the second semiconductor fin.
20. The device of claim 19 , wherein the spacer comprises a nitride material.