Field effect transistor structure comprising a stack of vertically separated channel nanowires
View Patent ↗A field effect transistor structure comprises a source and a drain on a substrate, and a stack of n vertically separated channel nanowires isolated from the substrate and connecting the source and the drain, where n is an integer and 2≦n≦20. The channel nanowires collectively comprise at least two different thicknesses and/or at least two different dopant concentrations and/or at least two different semiconductor materials.
1. A field effect transistor structure comprising:
a source and a drain on a substrate; and
a stack of n vertically separated channel nanowires isolated from the substrate and connecting the source and the drain, where n is an integer and 2≦n≦20, and where a vertical direction is substantially perpendicular to the substrate, the n vertically separated channel nanowires collectively comprising at least two different thicknesses and/or at least two different dopant concentrations and/or at least two different semiconductor materials.
2. The transistor structure of claim 1 , wherein the channel nanowires are arranged in the stack such that the thicknesses decrease in a direction away from the substrate.
3. The transistor structure of claim 1 , wherein the channel nanowires are arranged in the stack such that the dopant concentrations increase in a direction away from the substrate.
4. The transistor structure of claim 1 , wherein each of the semiconductor materials comprises a bandgap, and wherein the channel nanowires are arranged in the stack such that the bandgaps increase in a direction away from the substrate.
5. The transistor structure of claim 1 , wherein the n vertically separated channel nanowires comprise up to n different thicknesses and/or up to n different dopant concentrations and/or up to n different semiconductor materials.
6. The transistor structure of claim 1 , wherein the at least two different thicknesses are selected from about 1 nm to about 500 nm.
7. The transistor structure of claim 1 , wherein the at least two different dopant concentrations are selected from about 10 14 cm −3 to 10 19 cm −3 .
8. The transistor structure of claim 1 , wherein the at least two different semiconductor materials are selected from the group consisting of: GaAs, InAs, InP, GaP, InGaAs, InGaP, InSb, GaSb, InGaSb, InP, GaP, InGaP, InN, GaN, and InGaN.
9. The transistor structure of claim 1 , wherein the channel nanowires are vertically separated by a distance of from about 1 nm to about 100 nm.
10. The transistor structure of claim 1 , wherein the source and the drain comprise a dopant concentration of at least about 10 18 cm −3 .
11. The transistor structure of claim 1 , further comprising a gate electrode surrounding the channel nanowires and separated therefrom by a gate dielectric material, the gate electrode comprising a gate-all-around configuration.
12. The transistor structure of claim 1 , wherein the n vertically separated channel nanowires collectively comprise at least two different thicknesses.
13. The transistor structure of claim 1 , wherein the n vertically separated channel nanowires collectively comprise at least two different dopant concentrations.
14. The transistor structure of claim 1 , wherein the n vertically separated channel nanowires collectively comprise at least two different thicknesses and at least two different dopant concentrations.
15. The transistor structure of claim 14 , wherein the channel nanowires further comprise at least two different semiconductor materials.
16. The transistor structure of claim 1 , wherein the source and the drain are formed on the substrate by a regrowth process.
17. The transistor structure of claim 1 , wherein each of the n vertically separated channel nanowires comprise an n-type dopant.
18. The transistor structure of claim 1 , wherein each of the n vertically separated channel nanowires comprise a p-type dopant.
19. The transistor structure of claim 1 , further comprising a gate electrode adjacent to the stack of channel nanowires, wherein, over a gate bias (V gs ) range of at least about 300 mV, a transconductance (g m ) of the field effect transistor structure decreases less than about 10% from a maximum transconductance (g m,max ).
20. A MOSFET device comprising:
a source and a drain on a substrate;
a stack of n vertically separated channel nanowires isolated from the substrate and connecting the source and the drain, where n is an integer and 2≦n≦20, and where a vertical direction is substantially perpendicular to the substrate; and
a gate electrode adjacent to the stack of channel nanowires,
wherein, over a gate bias (V gs ) range of at least about 300 mV, a transconductance (g m ) of the MOSFET device decreases less than about 10% from a maximum transconductance (g m,max ).
21. The MOSFET device of claim 20 , wherein the n vertically separated channel nanowires collectively comprise at least two different thicknesses and/or at least two different dopant concentrations and/or at least two different semiconductor materials.
22. The MOSFET device of claim 20 , wherein the gate bias range is at least about 400 mV.
23. The MOSFET device of claim 20 , wherein the gate electrode surrounds the channel nanowires, the gate electrode comprising a gate-all-around configuration.
24. The MOSFET device of claim 20 , wherein the source and the drain comprise a dopant concentration of at least about 10 18 cm −3 .