Surface treatment to improve resistive-switching characteristics
This disclosure provides a method of fabricating a semiconductor device layer and associated memory cell structures. By performing a surface treatment process (such as ion bombardment) of a semiconductor device layer to create defects having a deliberate depth profile, one may create multistable memory cells having more consistent electrical parameters. For example, in a resistive-switching memory cell, one may obtain a tighter distribution of set and reset voltages and lower forming voltage, leading to improved device yield and reliability. In at least one embodiment, the depth profile is selected to modulate the type of defects and their influence on electrical properties of a bombarded metal oxide layer and to enhance uniform defect distribution.
1. A memory cell comprising:
a first layer operable as an electrode;
a second layer operable as an additional electrode;
a third layer operable as a defect access layer; and
a fourth layer operable as a semiconductor device layer;
wherein the third layer is disposed between the first layer and the fourth layer;
wherein the fourth layer is disposed between the second layer and the third layer;
wherein the fourth layer comprises a first region and a second region;
wherein the first region is closer to the third layer than the second region;
wherein the first region has a greater concentration of defects than the second region; and
wherein the first region comprises a non-metallic percolation path set by a forming voltage between the first layer and the second layer.
2. The memory device of claim 1 , wherein the first region comprises a transition metal oxide having a band gap greater than 4 eV.
3. The memory device of claim 1 , wherein the first region comprises one of hafnium oxide, aluminum oxide, titanium oxide, niobium oxide, or tantalum oxide.
4. The memory device of claim 1 , wherein the second region comprises a transition metal oxide having a band gap of greater than 4 eV.
5. The memory device of claim 1 , wherein the second region comprises one of hafnium oxide, aluminum oxide, titanium oxide, niobium oxide, or tantalum oxide.
6. The memory device of claim 1 , wherein the first region comprises a first transition metal oxide, wherein the second region comprises a second transition metal oxide, and wherein the first transition metal oxide is different from the second transition metal oxide.
7. The memory device of claim 1 , wherein the second region comprises one of scandium oxide or yttrium oxide.
8. The memory device of claim 1 , wherein the third layer increases an effective work function of the first layer.
9. The memory device of claim 1 , wherein the third layer and the second region both comprise a common material.
10. The memory device of claim 1 , wherein the fourth layer further comprises an interdiffused region disposed between the first region and the second region.
11. The memory device of claim 1 , wherein the defects comprise doping ions selected from the group consisting of lanthanum, oxygen, hafnium, cerium, praseodymium, neodymium, gadolinium, erbium, ytterbium, lutetium, hafnium, silicon, nitrogen, fluorine, chromium, titanium, tantalum, zirconium, aluminum, yttrium, molybdenum, scandium, niobium and vanadium.
12. The memory device of claim 1 , wherein the first region comprises hafnium oxide, and wherein the defects comprise oxygen ions.
13. The memory device of claim 1 , wherein the first region is contained within about 40% or less of a thickness of the fourth layer.
14. The memory device of claim 1 , wherein the first region is contained within about 25% or less of a thickness of the fourth layer.