Techniques for providing a semiconductor memory device
View Patent ↗Techniques for providing a semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as an apparatus including a first region and a second region. The apparatus may also include a body region disposed between the first region and the second region and capacitively coupled to a plurality of word lines, wherein each of the plurality of word lines is capacitively coupled to different portions of the body region.
1. A semiconductor memory device comprising:
a first region;
a second region; and
a body region disposed between the first region and the second region and capacitively coupled to a plurality of word lines, wherein each of the plurality of word lines is capacitively coupled to a respective portion of the body region, wherein the body region comprises an undoped semiconductor material.
2. The semiconductor memory device according to claim 1 , wherein the body region is electrically floating.
3. The semiconductor memory device according to claim 2 , wherein the first region comprises an P-doped semiconductor material.
4. The semiconductor memory device according to claim 3 , wherein the second region comprises an N-doped semiconductor material.
5. The semiconductor memory device according to claim 1 , wherein the first region, the second region, and the body region are formed on a substrate.
6. The semiconductor memory device according to claim 5 , wherein the first region, the second region, and the body region are arranged in a planar configuration on the substrate.
7. The semiconductor memory device according to claim 1 , wherein each of the plurality of word lines is capacitively coupled to a respective top portion on a top side of the body region.
8. The semiconductor memory device according to claim 1 , wherein the plurality of word lines further comprise a control word line.
9. The semiconductor memory device according to claim 1 , wherein the plurality of word lines comprise a first word line and a second word line.
10. The semiconductor memory device according to claim 9 , wherein the first word line is capacitively coupled to a first portion of the body region and the second word line is capacitively coupled to a second portion of the body region.
11. The semiconductor memory device according to claim 9 , wherein at least a portion of the first word line overlaps at least a portion of the second word line.
12. The semiconductor memory device according to claim 1 , wherein the first region is coupled to a bit line extending in a first orientation.
13. The semiconductor memory device according to claim 12 , wherein the second region is coupled to a source line extending in the first orientation.
14. The semiconductor memory device according to claim 13 , wherein the plurality of word lines are extending in a second orientation.
15. A semiconductor memory device comprising:
a first region;
a second region; and
a body region disposed between the first region and the second region and capacitively coupled to a plurality of word lines, wherein each of the plurality of word lines is capacitively coupled to a different portion of the body region, wherein a first of the plurality of word lines is formed on a first side of the body region and a second of the plurality of word lines is formed on a second side of the body region, wherein the second side is opposite the first side.
16. The semiconductor memory device according to claim 15 , wherein the body region is electrically floating.
17. The semiconductor memory device according to claim 16 , wherein the body region comprises an undoped semiconductor material.
18. The semiconductor memory device according to claim 17 , wherein the first region comprises an P-doped semiconductor material.
19. The semiconductor memory device according to claim 18 , wherein the second region comprises an N-doped semiconductor material.
20. The semiconductor memory device according to claim 15 , wherein the first region, the body region, the second region are formed in a sequential vertical configuration on a substrate.
21. The semiconductor memory device according to claim 15 , wherein each of the plurality of word lines is capacitively coupled to a respective side portion of the body region.
22. The semiconductor memory device according to claim 15 , wherein the plurality of word lines further comprise a control word line.
23. The semiconductor memory device according to claim 15 , wherein the first region is coupled to a bit line extending in a first orientation.
24. The semiconductor memory device according to claim 23 , wherein the second region is coupled to a source line extending in the first orientation.
25. The semiconductor memory device according to claim 24 , wherein the plurality of word lines are extending in a second orientation.