OFFLOADING OF COMPUTATION FOR RACK LEVEL SERVERS AND CORRESPONDING METHODS AND SYSTEMS
A distributed server system is disclosed that can handle multiple networked applications. A system can include at least one main processor; a plurality of offload processors connected to a memory bus; and a virtual switch respectively connected to the main processor and the plurality of offload processors using the memory bus, with the virtual switch configured to receive memory read/write data over the memory bus.
1 . A distributed server system for handling multiple networked applications, comprising:
at least one main processor;
a plurality of offload processors connected to a memory bus; and
a virtual switch respectively connected to the main processor and the plurality of offload processors using the memory bus, with the virtual switch configured to receive memory read/write data over the memory bus.
2 . The distributed server system of claim 1 , wherein the offload processors are configured to support a web server and the at least one main processor is configured to support for at least one selected from the group of: a server side script engine, a web page rendering engine, and a database engine.
3 . The distributed server system of claim 1 , wherein the offload processors are configured to support multimedia streaming data and the at least one main processor is configured to support an overlay control.
4 . The distributed server system of claim 1 , wherein the offload processors are configured to support a proxy server.
5 . The distributed server system of claim 1 , wherein the offload processors are connected to memory, and further include a snoop control unit configured for coherent read out and write in to memory.
6 . The distributed server system of claim 1 , wherein the offload processors are connected to memory and configured for zero-overhead context switching between threads of a networked application.
7 . The distributed server system of claim 1 , wherein the offload processors are connected to memory and a computational field programmable gate array (FPGA), all being mounted together on an inline module configured for insertion into a dual-in-line-memory-module (DIMM) socket.