OFFLOADING OF COMPUTATION FOR RACK LEVEL SERVERS AND CORRESPONDING METHODS AND SYSTEMS
A system is disclosed that can include at least one processor module connectable to a memory bus. The processor module can include at least one memory, at least one offload processor mounted on the processor module, and configured to execute operations on data received over the memory bus, and to output context data to the memory and read context data from the memory, and a hardware scheduling logic mounted on the module and configured to control operations of the at least one processor.
1 . A system, comprising:
at least one processor module connectable to a memory bus, the processor module including;
at least one memory,
at least one offload processor mounted on the processor module, and configured to execute operations on data received over the memory bus, and to output context data to the memory and read context data from the memory, and
a hardware scheduling logic mounted on the module and configured to control operations of the at least one processor.
2 . The system of claim 1 , further including:
an in-line module connector configured to physically connect the processor module to at least one in-line memory slot of a memory bus, with the in-line module connector being compatible with a dual-in-line-memory module (DIMM) connector.
3 . The system of claim 1 , wherein:
the memory bus comprises a double-data-rate (DDR) memory bus.
4 . The system module of claim 1 , further including:
at least one host processor coupled to the memory bus; and
the at least one processor module further includes an interface configured to receive write data and provide read data over the memory bus in response to a bus controller.
5 . The system of claim 4 , further including:
the interface comprises a direct memory access (DMA) slave.
6 . The system of claim 4 , further including:
an input/output device coupled to the at least one host processor via a host bus different than the memory bus.
7 . The system of claim 6 , wherein:
the input/output device is configured to transfer network packet data over the memory bus, the network packet data including a payload and a header portion.
8 . The system of claim 1 , further including:
an input/output memory management unit configured to translate logical read and write destinations to physical read and write destinations, the physical read and write destinations including locations of the at least one processor module.
9 . The system of claim 1 , further including:
at least one memory module that includes
an in-module connector configured to physically connect the memory module to one slot of the system memory bus, and
a plurality of memory integrated circuit devices configured to provide a physical memory addresses accessible via the system memory bus, including a ping-pong cache.