IP Library › Granted Patent US 9,087,817
Granted Patent B2
US 9,087,817 · App. 13/901,103 · Granted Jul 21, 2015

Semiconductor device including a gate wiring connected to at least one semiconductor chip

Inventors: Hisato Michikoshi (Osaka, JP); Noriyuki Hirakata (Osaka, JP); Hiroshi Notsu (Osaka, JP)
Assignee: Sumitomo Electric Industries, Ltd.
H01L23/48H01L23/49531H01L23/49562H01L23/49575H01L24/49H01L23/3107H01L24/45H01L24/48H01L2224/45014H01L2224/45124H01L2224/45144H01L2224/45147H01L2224/48195H01L2224/48247H01L2224/49111H01L2224/49175H01L2924/12032H01L2924/1305H01L2924/13055H01L2924/13091H01L2924/19107H01L2924/30107
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Quick Facts
Patent No.
US 9,087,817
App. No.
13/901,103
Granted
Jul 21, 2015
Kind
B2
Abstract

A semiconductor device includes at least one semiconductor chip, a gate wiring connected to the at least one semiconductor chip, a first wiring connected to the at least one semiconductor chip, and a second wiring connected to the at least one semiconductor chip. The first and second wirings extend along the gate wiring. The first wiring is arranged between the gate wiring and second wiring. The first wiring is the wiring closest to the gate wiring. A first part of the gate wiring opposing the first wiring is shorter than a second part of the gate wiring opposing the second wiring.

Claims (18)

1. A semiconductor device comprising:

at least one semiconductor chip;

a gate wiring connected to the at least one semiconductor chip;

a first wiring connected to the at least one semiconductor chip; and

a second wiring connected to the at least one semiconductor chip;

wherein the first and second wirings extend along the gate wiring;

wherein the first wiring is arranged between the gate wiring and second wiring;

wherein the first wiring is the wiring closest to the gate wiring;

wherein a first part of the gate wiring opposing the first wiring is shorter than a second part of the gate wiring opposing the second wiring;

wherein the at least one semiconductor chip comprises a plurality of semiconductor chips;

wherein the plurality of semiconductor chips are arranged along a first direction; and

wherein, with respect to an axis extending along a second direction perpendicular to the first direction between the semiconductor chips adjacent to each other, the gate wiring, first wiring, and second wiring on one side are arranged in the reverse of those on the other side.

2. The semiconductor device according to claim 1 , wherein the at least one semiconductor chip is made of a material containing a wide bandgap semiconductor.

3. The semiconductor device according to claim 1 , further comprising a wiring pattern connected to the gate wiring.

4. The semiconductor device according to claim 1 , further comprising:

a first lead electrically connected to the gate wiring;

a second lead electrically connected to the first and second wirings; and

a die pad having a chip mount surface for mounting the at least one semiconductor chip.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 23, 2013
From: MICHIKOSHI, HISATO; HIRAKATA, NORIYUKI; NOTSU, HIROSHI
To: SUMITOMO ELECTRIC INDUSTRIES, LTD.
Reel/Frame 030476/0643 →
Priority Claims (1)
JP 2012-145146 · Jun 28, 2012 · national
Continuity (2)
Provisional Application 61665761 · Jun 28, 2012
Related Publication 20140001481A1 · Jan 2, 2014