IP Library Granted Patent US 9,206,526
Granted Patent B2
US 9,206,526 · App. 13/901,298 · Granted Dec 8, 2015

Method for the formation of nano-scale on-chip optical waveguide structures

Inventor: Qing Liu (Guilderland, NY)
Assignee: STMicroelectronics, Inc.
C30B23/04C30B25/04C30B29/06G02B6/122G02B6/131G02B6/136G02B6/032G02B2006/12173G02B2006/12176
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Quick Facts
Patent No.
US 9,206,526
App. No.
13/901,298
Granted
Dec 8, 2015
Kind
B2
Abstract

A strip of sacrificial semiconductor material is formed on top of a non-sacrificial semiconductor material substrate layer. A conformal layer of the non-sacrificial semiconductor material is epitaxially grown to cover the substrate layer and the strip of sacrificial semiconductor material. An etch is performed to selectively remove the strip of sacrificial semiconductor material and leave a hollow channel surrounded by the conformal layer and the substrate layer. Using an anneal, the conformal layer and the substrate layer are reflowed to produce an optical waveguide structure including the hollow channel.

Claims (37)

1. A method, comprising:

forming a strip of sacrificial semiconductor material on top of a substrate layer formed of a non-sacrificial semiconductor material;

epitaxially growing a conformal layer of the non-sacrificial semiconductor material covering the substrate layer and the strip of sacrificial semiconductor material;

selectively removing the strip of sacrificial semiconductor material to leave a hollow channel surrounded by the conformal layer and the substrate layer; and

performing a reflow on the conformal layer and the substrate layer to produce an optical waveguide structure including said hollow channel.

2. The method of claim 1 , wherein the substrate layer is a top semiconductor layer of a silicon-on-insulator (SOI) substrate.

3. The method of claim 1 , wherein forming the strip of sacrificial semiconductor material further comprises forming an overlying layer of non-sacrificial semiconductor material over the strip of sacrificial semiconductor material.

4. The method of claim 3 , wherein epitaxially growing the conformal layer comprises epitaxially growing the conformal layer to also cover the overlying layer.

5. The method of claim 4 , wherein performing the reflow comprises performing the reflow on the conformal layer, the overlying layer and the substrate layer.

6. The method of claim 1 , wherein a bottom portion of the hollow channel is positioned below an upper surface of the reflowed substrate layer.

7. The method of claim 1 , wherein the optical waveguide structure has a width of about 100 nm to hundreds of nanometers and wherein said hollow channel has a cross-sectional diameter of about 50 nm to hundreds of nanometers.

8. A method, comprising:

forming a mask over a substrate layer formed of a first semiconductor material;

forming an opening in the mask to expose a top surface of the first semiconductor material substrate layer;

epitaxially growing a sacrificial layer formed of a second semiconductor material in said opening above the top surface of the first semiconductor material substrate layer;

patterning the sacrificial layer into at least one line of sacrificial semiconductor material;

epitaxially growing a conformal layer of first semiconductor material covering the first semiconductor material substrate layer and the at least one line of sacrificial semiconductor material;

selectively removing the at least one line of sacrificial semiconductor material to leave a hollow channel surrounded by the conformal layer and the first semiconductor material substrate layer; and

performing a reflow on the conformal layer and the first semiconductor material substrate layer to produce an optical waveguide structure including said hollow channel.

9. The method of claim 8 , wherein the silicon semiconductor substrate layer is a top semiconductor layer of a silicon-on-insulator (SOI) substrate.

10. The method of claim 8 , wherein the hollow channel of the optical waveguide structure has a substantially circular cross-section.

11. The method of claim 8 , further comprising epitaxially growing an overlying layer of the first semiconductor material over the sacrificial layer formed of the second semiconductor material.

12. The method of claim 11 , wherein patterning comprises patterning the overlying layer and sacrificial layer and wherein epitaxially growing the conformal layer comprises epitaxially growing the conformal layer to also cover the overlying layer.

13. The method of claim 11 , wherein performing the reflow comprises performing the reflow on the conformal layer, the overlying layer and the first semiconductor material substrate layer.

14. The method of claim 8 , wherein a bottom portion of the hollow channel is positioned below an upper surface of the reflowed substrate layer.

15. The method of claim 8 , wherein the optical waveguide structure has a width of about 100 nm to hundreds of nanometers and wherein said hollow channel has a cross-sectional diameter of about 50 nm to hundreds of nanometers.

16. A method, comprising:

on a substrate layer formed of a first semiconductor material, epitaxially growing a sacrificial layer formed of a second semiconductor material;

epitaxially growing an overlying layer formed of the first semiconductor material on top of the sacrificial layer;

forming parallel trenches extending through the sacrificial layer and overlying layer to reach at least a top surface of the substrate layer, the parallel trenches defining an interposed material strip made from the epitaxially grown layers of the first and second semiconductor materials;

epitaxially growing a conformal layer of first semiconductor material covering the interposed material strip;

selectively removing the second semiconductor material of the sacrificial layer from the interposed material strip to leave a hollow channel surrounded by the conformal layer and the substrate layer; and

performing a reflow on the conformal layer, overlying layer and substrate layer to produce an optical waveguide structure including said hollow channel.

17. The method of claim 16 , wherein the substrate layer is a top semiconductor layer of a silicon-on-insulator (SOI) substrate.

18. The method of claim 16 , wherein forming parallel trenches comprises forming parallel trenches extending through the sacrificial layer and overlying layer to reach at least a top surface of the substrate layer.

19. The method of claim 16 , wherein a bottom portion of the hollow channel is positioned below an upper surface of the reflowed substrate layer.

20. The method of claim 16 , wherein the optical waveguide structure has a width of about 100 nm to hundreds of nanometers and wherein said hollow channel has a cross-sectional diameter of about 50 nm to hundreds of nanometers.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 25, 2022
From: STMICROELECTRONICS, INC.
To: STMICROELECTRONICS INTERNATIONAL N.V.
Reel/Frame 060177/0226 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 23, 2013
From: LIU, QING
To: STMICROELECTRONICS, INC.
Reel/Frame 030477/0879 →
Continuity (1)
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