Hybrid phase-locked loops
View Patent ↗A method of controlling a hybrid phase-locked loop may include generating a first control signal based on an offset signal and a second control signal and determining a difference between the first and the second control signals. The method may further include adjusting a value of the offset signal based on the difference between the first and the second control signals to drive a level of the first control signal to a level of the second control signal. The method may further include determining when the level of the first control signal crosses the level of the second control signal. After the level of the first control signal crosses the level of the second control signal, the method may include adjusting the value of the offset signal based on a number of occurrences of the level of the first control signal crossing the level of the second control signal.
1. A circuit comprising:
an analog control signal unit configured to generate a first analog control signal based on an offset signal;
a sampler digitizer configured to determine a difference between the first analog control signal and a second analog control signal and to generate a difference level signal with a value based on the determined difference between the first analog control signal and the second analog control signal;
a crossing detector configured to determine when the level of the first analog control signal crosses the level of the second analog control signal based on the difference level signal; and
a gain unit configured to apply a gain to the difference level signal to generate the offset signal based on a number of occurrences of the level of the first analog control signal crossing the level of the second analog control signal.
2. The circuit of claim 1 , wherein the sampler digitizer is further configured to determine a plurality of difference level signals, wherein the crossing detector determines when the level of the first analog control signal crosses the level of the second analog control signal based on a majority of the values of the difference level signals being between a threshold and zero during a voting period of time.
3. The circuit of claim 2 , wherein the sampler digitizer adjusts the value of the difference level signal to be least significant when the difference between the first analog control signal and the second analog control signal is between the threshold and zero.
4. The circuit of claim 1 , wherein the gain unit is configured to reduce the gain applied to the difference level signal for each occurrence of the level of the first analog control signal crossing the level of the second analog control signal.
5. The circuit of claim 1 , further comprising an oscillator configured to generate an output signal based on the second analog control signal and a digital control signal provided by a digital phase-locked loop that includes the oscillator.
6. The circuit of claim 5 , further comprising a divider configured to divide the output signal based on the offset signal to generate a feedback signal, the analog control signal unit configured to generate the first analog control signal based on the feedback signal.
7. The circuit of claim 5 , further comprising a coupling unit configured to provide the first analog control signal to the oscillator in place of the second analog control signal after the number of occurrences of the level of the first analog control signal crossing the level of the second analog control signal exceeds a threshold.