IP Library Granted Patent US 9,224,436
Granted Patent B2
US 9,224,436 · App. 13/902,591 · Granted Dec 29, 2015

Apparatuses including a memory array with separate global read and write lines and/or sense amplifier region column select line and related methods

Inventors: Harish N. Venkata (Allen, TX); John F. Schreck (Lucas, TX); Mansour Fardad (Allen, TX)
Assignee: Micron Technology, Inc.
G11C7/065G11C7/18G11C7/12
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Quick Facts
Patent No.
US 9,224,436
App. No.
13/902,591
Granted
Dec 29, 2015
Kind
B2
Abstract

Apparatuses and methods for memory arrays with separate global read and write lines and/or sense amplifier region column select lines are disclosed. An example apparatus includes first and second memory sections, and further includes a sense amplifier region. A memory section includes a word line extending in a first direction and a digit line extending in a second direction, and the sense amplifier region is disposed between the first and second memory sections. The sense amplifier region includes a sense amplifier coupled to the digit line, a local input/output (LIO) line, a column select circuit coupled to the sense amplifier, and a column select line. The column select line extends in the first direction and is configured to provide a column select signal to the column select circuit. Capacitance of a LIO line may be reduced by coupling fewer sense amplifiers of a group to the LIO line.

Claims (31)

1. An apparatus, comprising:

first and second memory sections, each memory section including a wordline extending in a first direction and a digit line extending in a second direction perpendicular to the first direction;

a global read line and a separate global write line extending over the first and second memory sections in the second direction;

a read/write circuit comprising:

a data amplifier coupled to the global read line and configured to amplify read data from the memory sections via the global read line; and

a write data driver configured to drive write data and to provide the write data to the memory sections via the global write line;

a sense amplifier region disposed between the first and second memory sections, the sense amplifier region including:

a sense amplifier coupled to the digit line;

a local input/output line;

a column select circuit coupled to the sense amplifier and configured to couple the sense amplifier to the local input/output line responsive to an active column select signal; and

a column select line coupled to the column select circuit and configured to provide a column select signal to the column select circuit, wherein the column select line extends in the first direction which is perpendicular to a global read line and a separate global write line,

wherein the global write line is configured to provide the write data which is amplified by the write data driver.

2. The apparatus of claim 1 , further comprising:

a local read/write circuit, coupled to a global read line and a separate global write line, the local read/write circuit configured to provide data from the local input/output line to the global read line and further configured to provide data from the global write line to the local input/output line.

3. The apparatus of claim 2 wherein the sense amplifier region further includes a plurality of groups of sense amplifier circuits, each group coupled to a respective local read/write circuit.

4. The apparatus of claim 3 wherein the respective local read/write circuit comprises:

a read circuit coupled to the local input/output line and configured to couple a signal line of the global read line to a read voltage based at least in part on a first voltage difference on the local input/output line; and

a write circuit coupled to the local input/output line and configured to couple global write line to the local input/output line responsive to being activated to provide a second voltage difference to the local input/output line.

5. The apparatus of claim 4 wherein the same read voltage is provided to the local read/write circuits included in the sense amplifier region.

6. The apparatus of claim 1 wherein the read/write circuit further comprises:

precharge circuits configured to precharge the global read line to a precharge voltage.

7. The apparatus of claim 6 wherein the precharge voltage is a high voltage level.

8. The apparatus of claim 6 wherein the precharge voltage is an intermediate voltage level.

9. The apparatus of claim 6 , wherein each precharge circuit comprises:

a pair of precharge switches coupled to the digit line and a precharge voltage; and

an equilibration switch coupled to the digit line.

10. The apparatus of claim 1 wherein the global read line is a first differential pair of signal lines and the global write line is a second differential pair of signal lines.

11. The apparatus of claim 1 wherein the digit line is a first differential pair of signal lines and the local input/output line is a second differential pair of signal lines.

12. The apparatus of claim 1 wherein the sense amplifier is one of a plurality of sense amplifiers included in the sense amplifier region, wherein the column select circuit is one of a plurality of column select circuits, and wherein the column select line is one of a plurality of column select lines, each of the plurality of column select circuits coupled to a respective one of the plurality of sense amplifiers and further coupled to a respective one of the plurality of column select lines, each of the plurality of column select circuits configured to couple the respective one of the plurality of sense amplifiers to the local input/output line responsive to an active column select signal provided on the respective one of the plurality of column select lines.

13. The apparatus of claim 1 wherein the plurality of column select lines extend in the first direction and are included in the sense amplifier region.

14. The apparatus of claim 1 wherein the sense amplifier region further includes a precharge circuit coupled to the sense amplifier and the digit line, the precharge circuit configured to precharge and equilibrate the digit line responsive to an active precharge signal.

Assignments (8)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050937/0001 →
RELEASE OF SECURITY INTEREST Recorded Aug 23, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047243/0001 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Jun 8, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 043079/0001 →
PATENT SECURITY AGREEMENT Recorded Jun 2, 2016
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 038954/0001 →
SECURITY INTEREST Recorded May 12, 2016
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 038669/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 24, 2013
From: VENKATA, HARISH N.; SCHRECK, JOHN F.; FARDAD, MANSOUR
To: MICRON TECHNOLOGY, INC.
Reel/Frame 030485/0519 →
Continuity (1)
Related Publication 20140347945A1 · Nov 27, 2014