Distributed on-chip decoupling apparatus and method using package interconnect
An integrated circuit device is disclosed. The integrated circuit device includes a semiconductor die fabricated by a front-end semiconductor process and having oppositely disposed planar surfaces. The semiconductor die is formed with semiconductor devices, power supply circuitry coupled to the semiconductor devices, decoupling capacitance circuitry, and through-vias. The through-vias include a first group of vias coupled to the power supply circuitry and a second group of vias coupled to the decoupling capacitance circuitry. Conductors are formed in a first metal layer disposed on the semiconductor die in accordance with a back-end semiconductor process. The conductors are configured to couple to the first and second groups of through-vias to establish conductive paths from the power supply circuitry to the decoupling capacitance circuitry.
1. A semiconductor device comprising:
an integrated circuit memory device including
a semiconductor memory die formed with a first group of storage circuits, the first group of storage circuits distributed across the semiconductor memory die in a first spaced-apart pattern; and
an integrated circuit memory controller stacked with the integrated circuit memory device, the integrated circuit memory controller including
a semiconductor controller die formed with a first group of interface circuits distributed across the semiconductor controller die in a second pattern that substantially aligns with the first group of storage circuits, the semiconductor controller die formed with a third circuit separate from the first group of interface circuits and a first group of through-vias that couple to the first group of interface circuits, and to the third circuit,
back-end metal formed on the semiconductor controller die to electrically contact the through-vias to complete one or more conductive paths that couple the second group of interface circuits to the third circuit.
2. The semiconductor device of claim 1 wherein:
the second group of interface circuits includes power supply circuitry; and
the third circuit comprises decoupling capacitance circuitry.
3. The semiconductor device of claim 1 wherein:
the semiconductor memory die comprises a plurality of memory dies disposed in a stacked arrangement and interconnected by respective groups of through-silicon-vias.
4. The semiconductor device of claim 3 further comprising:
a substrate having first and second oppositely disposed planar sides;
an integrated circuit logic controller disposed on the first substrate planar side; and
wherein the integrated circuit memory device and the integrated circuit memory controller are mounted on the second substrate planar side.
5. The semiconductor device of claim 1 wherein the back-end metal comprises a back-side metal (BSM) layer.
6. The semiconductor device of claim 5 wherein:
the BSM includes striped ground and power paths.
7. The semiconductor device of claim 5 wherein the back-end metal comprises a redistribution (RDL) layer.
8. The semiconductor device of claim 7 wherein the RDL includes striped ground and power paths.
9. The semiconductor device of claim 1 wherein the back-end metal comprises:
a first back-side metal (BSM) layer for routing ground signal paths; and
a redistribution layer (RDL) for routing power signal paths, the RDL formed in an overlying relationship with the BSM.
10. The semiconductor device of claim 1 and further comprising:
an integrated circuit logic controller coupled to the integrated circuit memory controller.
11. The semiconductor device of claim 10 wherein:
the integrated circuit logic controller and the integrated circuit memory controller are formed on the same integrated circuit chip.