Nanovolt amplifier design
A circuit can include operational amplifier having a first input, a second input, and an output, first and second resistors in series between the output of the op-amp and a ground, and multiple switches configurable to toggle the circuit between a positive phase and a negative phase.
1. A circuit, comprising:
an operational amplifier (op-amp) having a first input (+), a second input (−), and an output having an output voltage V OUT , wherein there is an offset voltage V OS between the first and second inputs of the op-amp;
a first resistor R 1 having a first end electrically coupled to the output of the op-amp and a second end;
a second resistor R 2 electrically coupled between the second end of the first resistor and a ground;
a first switch having a first position in which the first input (+) of the op-amp is electrically coupled to a first input source (Hi) and a second position in which the second input (−) of the op-amp is electrically coupled to the first input source (Hi);
a second switch having a first position in which the output of the op-amp is electrically coupled to the second input (−) of the op-amp and a second position in which the output of the op-amp is electrically coupled to a second input source (Lo); and
a third switch having a first position in which the second input source (Lo) is electrically coupled to the second end of the first resistor and a second position in which the first input source (Hi) is electrically coupled to the second end of the first resistor, wherein there is an input voltage V IN between the first and second input sources, and wherein there is a thermal voltage (V T1 ) at the second end of the first resistor.
2. The circuit of claim 1 , wherein the circuit is in a positive phase when each of the first, second, and third switches is in the first position.
3. The circuit of claim 2 , wherein the output voltage V OUT is V OUT+ when the circuit is in the positive phase, and further wherein a sum of the output voltage V OUT+ and a measured offset voltage V Mos is determined by the following:
V
OUT
+
+
V
MOS
=
(
+
V
IN
+
V
OS
+
V
T
1
)
(
R
1
+
R
2
R
1
)
+
V
MOS
.
4. The circuit of claim 3 , wherein the circuit is in a negative phase when each of the first, second, and third switches is in the second position.
5. The circuit of claim 4 , wherein the output voltage V OUT is V OUT− when the circuit is in the negative phase, and further wherein a sum of the output voltage V OUT− and the measured offset voltage V Mos is determined by the following:
V
OUT
-
+
V
MOS
=
(
-
V
IN
+
V
OS
+
V
T
1
)
(
R
1
+
R
2
R
1
)
+
V
MOS
6. The circuit of claim 5 , wherein a measurement voltage V Meas may be determined by the following:
V
Meas
=
(
V
OUT
+
-
V
OUT
)
2
=
V
IN
(
R
1
+
R
2
R
1
)
7. A circuit, comprising:
a first operational amplifier (op-amp) having a first input (+), a second input (−), and an output, wherein there is a first offset voltage V OS-A between the first and second inputs of the first op-amp;
a first resistor R 1 having a first end electrically coupled to the output of the op-amp and a second end;
a second op-amp having a first input electrically coupled to a ground, a second input (−), and an output, wherein there is a second offset voltage V OS-B between the first and second inputs of the second op-amp;
a second resistor R 2 electrically coupled between the second end of the first resistor and the output of the second op-amp;
a first switch having a first position in which the first input (+) of the first op-amp is electrically coupled to a first input source (Hi) and a second position in which the second input (−) of the first op-amp is electrically coupled to the first input source (Hi);
a second switch having a first position in which the output of the first op-amp is electrically coupled to the second input (−) of the second op-amp and a second position in which the second input (−) of the second op-amp is electrically coupled to the first input source (Hi); and
a third switch having a first position in which the second end of the first resistor is electrically coupled to the second input source (Lo) and a second position in which the second end of the first resistor is electrically coupled to the second input (−) of the second op-amp, wherein there is an input voltage V IN between the first and second input sources, wherein there is a thermal voltage (V T1 ) at the second end of the first resistor, and further wherein there is an output voltage V OUT between the outputs of the first and second op-amps.
8. The circuit of claim 7 , wherein the circuit is in a positive phase when each of the first, second, and third switches is in the second position.
9. The circuit of claim 7 , further comprising a capacitance between the first input of the second op-amp and a chassis.
10. The circuit of claim 7 , further comprising a guard around the circuit.
11. The circuit of claim 10 , wherein the guard is a Faraday cage.
12. The circuit of claim 10 , further comprising a capacitance between the guard and a chassis.
13. The circuit of claim 7 , further comprising at least one additional resistor electrically positioned between the first and second resistors.
14. The circuit of claim 13 , further comprising a guard around the circuit.
15. The circuit of claim 8 , further comprising a third op-amp electrically coupled to the second end of the first resistor, a second input, and an output, wherein there is a third offset voltage V OS-C between the first and second inputs of the third op-amp.
16. The circuit of claim 15 , wherein the output voltage V OUT is V OUT-P when the circuit is in the positive phase, and further wherein a sum of the output voltage V OUT-p and a measured offset voltage V Mos is determined by the following:
V
Meas
-
P
=
V
OUT
-
P
+
V
MOS
=
(
V
IN
+
V
OS
-
A
+
V
OS
-
C
+
V
T
1
)
(
R
1
+
R
2
R
1
)
+
V
MOS
17. The circuit of claim 16 , wherein the circuit is in a negative phase when each of the first, second, and third switches is in the first position.
18. The circuit of claim 17 , wherein the output voltage V OUT is V OUT-N when the circuit is in the negative phase, and further wherein a sum of the output voltage V OUT-N and the measured offset voltage V Mos is determined by the following:
V
Meas
-
N
=
V
OUT
-
N
+
V
MOS
=
(
-
V
IN
+
V
OS
-
A
+
V
OS
-
C
+
V
T
1
)
(
R
1
+
R
2
R
1
)
+
V
MOS
19. The circuit of claim 18 , wherein the resulting output voltage V OUT may be determined by the following:
V
OUT
=
1
2
(
V
OUT
-
P
+
V
MOS
-
V
OUT
-
N
-
V
MOS
)
=
V
IN
(
R
1
+
R
2
R
1
)
.