Signal duty cycle reduction

1. A circuit comprising:

one or more inputs configured to receive a positive in-phase (“I”)-channel signal (“I+ signal”), a negative I-channel signal (“I− signal”), a positive quadrature-phase (“Q”)-channel signal (“Q+ signal”), and a negative Q-channel signal (“Q− signal”);

one or more outputs configured to output a positive truncated I-channel signal (“truncated I+ signal”), a negative truncated I-channel signal (“truncated I− signal”), a positive truncated Q-channel signal (“truncated Q+ signal”), and a negative truncated Q-channel signal (“truncated Q− signal”), the truncated I+ signal having a reduced duty cycle with respect to the I+ signal, the truncated I− signal having a reduced duty cycle with respect to the I− signal, the truncated Q+ signal having a reduced duty cycle with respect to the Q+ signal, and the truncated Q− signal having a reduced duty cycle with respect to the Q− signal;

a first logic gate configured to perform a logic operation with respect to the I+ signal, the Q+ signal, and a complement of the truncated Q− signal to generate the truncated I+ signal;

a second logic gate configured to perform the logic operation with respect to the I− signal, the Q− signal, and a complement of the truncated Q+ signal to generate the truncated I− signal;

a third logic gate configured to perform the logic operation with respect to the I− signal, the Q+ signal, and a complement of the truncated I+ signal to generate the truncated Q+ signal; and

a fourth logic gate configured to perform the logic operation with respect to the I+ signal, the Q− signal, and a complement of the truncated I− signal to generate the truncated Q− signal.

2. The circuit of claim 1 , wherein:

the first logic gate is configured to output the complement of the truncated I+ signal;

the second logic gate is configured to output the complement of the truncated I− signal;

the third logic gate is configured to output the complement of the truncated Q+ signal; and

the fourth logic gate is configured to output the complement of the truncated Q− signal.

3. The circuit of claim 2 , wherein the logic operation includes an AND operation or an OR operation.

4. The circuit of claim 2 , further comprising:

a first inverter configured to generate the truncated I+ signal based on the complement of the truncated I+ signal output by the first logic gate;

a second inverter configured to generate the truncated I− signal based on the complement of the truncated I− signal output by the second logic gate;

a third inverter configured to generate the truncated Q+ signal based on the complement of the truncated Q+ signal output by the third logic gate; and

a fourth inverter configured to generate the truncated Q− signal based on the complement of the truncated Q− signal output by the fourth logic gate.

5. The circuit of claim 1 , wherein one or more of the truncated I+ signal, the truncated I− signal, the truncated Q+ signal, and the truncated Q− signal has a duty cycle of 25% or less.

6. The circuit of claim 1 , further comprising a divider module configured to generate the I+ signal, the I− signal, the Q+ signal, and the Q− signal based on a clock signal generated by a voltage controlled oscillator (“VCO”).

7. The circuit of claim 6 , wherein the VCO is configured to generate the clock signal at a frequency that is associated with demodulating a wireless communication signal.

8. A circuit comprising:

one or more inputs configured to receive a positive in-phase (“I”)-channel signal (“I+ signal”), a negative I-channel signal (“I− signal”), a positive quadrature-phase (“Q”)-channel signal (“Q+ signal”), and a negative Q-channel signal (“Q− signal”);

one or more outputs configured to output a positive truncated I-channel signal (“truncated I+ signal”), a negative truncated I-channel signal (“truncated I− signal”), a positive truncated Q-channel signal (“truncated Q+ signal”), and a negative truncated Q-channel signal (“truncated Q− signal”), the truncated I+ signal having a reduced duty cycle with respect to the I+ signal, the truncated I− signal having a reduced duty cycle with respect to the I− signal, the truncated Q+ signal having a reduced duty cycle with respect to the Q+ signal, and the truncated Q− signal having a reduced duty cycle with respect to the Q− signal; and

a duty control module configured to:

generate the truncated I+ signal based on the I+ signal, the Q+ signal, and a complement of the truncated Q− signal;

generate the truncated I− signal based on the I− signal, the Q− signal, and a complement of the truncated Q+ signal;

generate the truncated Q+ signal based on the I− signal, the Q+ signal, and a complement of the truncated I+ signal; and

generate the truncated Q− signal based on the I+ signal, the Q− signal, and a complement of the truncated I− signal.

9. The circuit of claim 8 , wherein the duty control module further comprises:

a first logic gate configured to perform a logic operation with respect to the I+ signal, the Q+ signal, and the complement of the truncated Q− signal to generate the truncated I+ signal;

a second logic gate configured to perform the logic operation with respect to the I− signal, the Q− signal, and the complement of the truncated Q+ signal to generate the truncated I− signal;

a third logic gate configured to perform the logic operation with respect to the I− signal, the Q+ signal, and the complement of the truncated I+ signal to generate the truncated Q+ signal; and

a fourth logic gate configured to perform the logic operation with respect to the I+ signal, the Q− signal, and the complement of the truncated I− signal to generate the truncated Q− signal.

10. The circuit of claim 9 , wherein the logic operation includes an AND operation or an OR operation.

11. The circuit of claim 9 , wherein the first logic gate is configured to output the complement of the truncated I+ signal, the second logic gate is configured to output the complement of the truncated I− signal, the third logic gate is configured to output the complement of the truncated Q+ signal, and the fourth logic gate is configured to output the complement of the truncated Q− signal, the circuit further comprising:

a first inverter configured to generate the truncated I+ signal based on the complement of the truncated I+ signal output by the first logic gate;

a second inverter configured to generate the truncated I− signal based on the complement of the truncated I− signal output by the second logic gate;

a third inverter configured to generate the truncated Q+ signal based on the complement of the truncated Q+ signal output by the third logic gate; and

a fourth inverter configured to generate the truncated Q− signal based on the complement of the truncated Q− signal output by the fourth logic gate.

12. The circuit of claim 8 , wherein one or more of the truncated I+ signal, the truncated I− signal, the truncated Q+ signal, and the truncated Q− signal has a duty cycle of 25% or less.

13. The circuit of claim 8 , further comprising a divider module configured to generate the I+ signal, the I− signal, the Q+ signal, and the Q− signal based on a clock signal generated by a voltage controlled oscillator (“VCO”).

14. The circuit of claim 13 , wherein the VCO is configured to generate the clock signal at a frequency that is associated with demodulating a wireless communication signal.

15. A method of reducing a duty cycle of one or more signals, the method comprising:

receiving a positive in-phase (“I”)-channel signal (“I+ signal”), a negative I-channel signal (“I− signal”), a positive quadrature-phase (“Q”)-channel signal (“Q+ signal”), and a negative Q-channel signal (“Q− signal”);

outputting a positive truncated I-channel signal (“truncated I+ signal”), a negative truncated I-channel signal (“truncated I− signal”), a positive truncated Q-channel signal (“truncated Q+ signal”), and a negative truncated Q-channel signal (“truncated Q− signal”), the truncated I+ signal having a reduced duty cycle with respect to the I+ signal, the truncated I− signal having a reduced duty cycle with respect to the I− signal, the truncated Q+ signal having a reduced duty cycle with respect to the Q+ signal, and the truncated Q− signal having a reduced duty cycle with respect to the Q− signal;

generating the truncated I+ signal based on the I+ signal, the Q+ signal, and a complement of the truncated Q− signal;

generating the truncated I− signal based on the I− signal, the Q− signal, and a complement of the truncated Q+ signal;

generating the truncated Q+ signal based on the I− signal, the Q+ signal, and a complement of the truncated I+ signal; and

generating the truncated Q− signal based on the I+ signal, the Q− signal, and a complement of the truncated I− signal.

16. The method of claim 15 , further comprising:

performing an a logic operation with respect to the I+ signal, the Q+ signal, and the complement of the truncated Q− signal to generate the truncated I+ signal;

performing the logic operation with respect to the I− signal, the Q− signal, and the complement of the truncated Q+ signal to generate the truncated I− signal;

performing the logic operation with respect to the I− signal, the Q+ signal, and the complement of the truncated I+ signal to generate the truncated Q+ signal; and

performing the logic operation with respect to the I+ signal, the Q− signal, and the complement of the truncated I− signal to generate the truncated Q− signal.

17. The method of claim 16 , wherein the logic operation includes an AND operation or an OR operation.

18. The method of claim 15 , wherein one or more of the truncated I+ signal, the truncated I− signal, the truncated Q+ signal, and the truncated Q− signal has a duty cycle of 25% or less.

19. The method of claim 15 , further comprising generating the I+ signal, the I− signal, the Q+ signal, and the Q− signal based on a clock signal.

20. The method of claim 19 , further comprising generating the clock signal at a frequency that is associated with demodulating a wireless communication signal.