Semiconductor device
A well voltage supply cell includes third gate electrode group (including a third gate electrode corresponding to a first gate electrode) located symmetrically to first gate electrode group (including the first gate electrode constituting an access transistor) of a first SRAM cell, fourth gate electrode group (including a fourth gate electrode corresponding to a second gate electrode) located symmetrically to second gate electrode group (including the second gate electrode constituting an access transistor) of a second SRAM cell. a P-type impurity diffusion region located on a P well between the third gate electrode and the fourth gate electrode located opposite to each other, a first N-type impurity diffusion region located on the side of the third gate electrode closer to the first SRAM cell, and a second N-type impurity diffusion region located on the side of the fourth gate electrode closer to the second SRAM cell.
1. A semiconductor device comprising:
a first SRAM cell including a first gate electrode group lying in a first direction on a P well and an N well, the first gate electrode group including a first gate electrode constituting an access transistor;
a second SRAM cell including a second gate electrode group located symmetrically to the first gate electrode group with respect to an axis in the first direction, the second gate electrode group including a second gate electrode constituting an access transistor; and
a first well voltage supply cell located between the first SRAM cell and the second SRAM cell in a direction perpendicular to the first direction and supplying voltages to the P well and the N well,
wherein the first well voltage supply cell includes:
a third gate electrode group located symmetrically to the first gate electrode group with respect to a border line with the first SRAM cell located adjacently and including a third gate electrode corresponding to the first gate electrode;
a fourth gate electrode group located symmetrically to the second gate electrode group with respect to a border line with the second SRAM cell located adjacently and including a fourth gate electrode corresponding to the second gate electrode;
a P-type impurity diffusion region located on the P well between the third gate electrode and the fourth gate electrode located opposite to each other;
a first N-type impurity diffusion region located on a side of the third gate electrode closer to the first SRAM cell; and
a second N-type impurity diffusion region located on a side of the fourth gate electrode closer to the second SRAM cell.
2. The semiconductor device according to claim 1 , wherein another gate electrode is not located between the third gate electrode and the fourth gate electrode located opposite to each other.
3. The semiconductor device according to claim 1 , wherein the first N-type impurity diffusion region is formed in contact with the third gate electrode, and the second N-type impurity diffusion region is formed in contact with the fourth gate electrode.
4. The semiconductor device according to claim 1 , wherein the first well voltage supply cell further includes a third N-type impurity diffusion region located on the N well between the third gate electrode group and the fourth gate electrode group.
5. The semiconductor device according to claim 1 , wherein the P-type impurity diffusion region is formed in contact with the third gate electrode and the fourth gate electrode.
6. The semiconductor device according to claim 5 , wherein a P-type impurity concentration of the third gate electrode is higher than a P-type impurity concentration of the first gate electrode.
7. The semiconductor device according to claim 5 , wherein a P-type impurity concentration of the fourth gate electrode is higher than a P-type impurity concentration of the second gate electrode.
8. The semiconductor device according to claim 1 , wherein a first low-voltage power supply voltage to be supplied to the P well through the P-type impurity diffusion region is lower than a second low-voltage power supply voltage to cause transistors in the first and second SRAM cells to operate.
9. The semiconductor device according to claim 4 , wherein a first high-voltage power supply voltage to be supplied to the N well through the third N-type impurity diffusion region is higher than a second high-voltage power supply voltage to operate transistors in the first and second SRAM cells.
10. The semiconductor device according to claim 1 , further comprising:
a second well voltage supply cell located adjacent to the first well voltage supply cell in the first direction, wherein
the first well voltage supply cell and the second well voltage supply cell are arranged line-symmetrically with respect to a border line.
11. The semiconductor device according to claim 4 , wherein the third N-type impurity diffusion region is formed protruding toward the first direction.
12. The semiconductor device according to claim 4 , wherein each of the third gate electrode and the fourth gate electrode forms a parasitic diode.