IP Library Granted Patent US 8,952,761
Granted Patent B2
US 8,952,761 · App. 13/911,876 · Granted Feb 10, 2015

System and method for supporting different types of oscillator circuits

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 8,952,761
App. No.
13/911,876
Granted
Feb 10, 2015
Kind
B2
Abstract

In accordance with some embodiments of the present disclosure, an oscillator circuit comprises, a first pad associated with a first terminal of an oscillator and a second pad associated with a second terminal of the oscillator. The oscillator is configured to generate an oscillating signal and communicate the oscillating signal from the second terminal to a clock distributor coupled to the second pad. The oscillator circuit further comprises an oscillator gain element comprising an output node coupled to the first pad and an input node coupled to the second pad. The oscillator circuit also comprises a digital-to-analog converter (DAC) coupled to the first pad. The oscillator circuit additionally comprises a switching circuit coupled to the gain element. The switching circuit is configured to enable the gain element when the oscillator comprises a resonator and disable the gain element when the oscillator comprises a voltage controlled oscillating module.

Claims (9)

1. An oscillator circuit comprising:

a gain element including:

a first transistor including a first gate, a first source, a first drain and a first well; and

a second transistor including a second gate, a second source, a second drain and a second well; and

a switching circuit configured to tie the first and second gates, the first and second sources, the first and second drains, and the first and second wells of the gain element such that a voltage at the first and second gates, the first and second sources, the first and second drains and the first and second wells is approximately the same to disable the gain element.

2. The oscillator circuit of claim 1 , the switching circuit configured to disable the gain element when an oscillator associated with the oscillator circuit comprises a voltage controlled oscillator module.

3. The oscillator circuit of claim 1 , the switching circuit configured to enable the gain element when an oscillator associated with the oscillator circuit comprises a resonator.

4. The oscillator circuit of claim 1 , further comprising a pad associated with a terminal of an oscillator, the switching circuit further comprising a switch coupled between the pad and an input node of the gain element, the switch configured to decouple the input node of the gain element with the pad when disabling the gain element.

5. The oscillator circuit of claim 4 , the switch further configured to couple the input node of the gain element with the pad when the oscillator comprises a resonator.

Assignments (5)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 26, 2020
From: INTEL CORPORATION
To: APPLE INC.
Reel/Frame 053062/0703 →
CONFIRMATORY ASSIGNMENT Recorded Jun 25, 2020
From: INTEL IP CORPORATION
To: INTEL CORPORATION
Reel/Frame 053066/0388 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 28, 2013
From: FUJITSU SEMICONDUCTOR WIRELESS PRODUCTS, INC.
To: INTEL IP CORPORATION
Reel/Frame 031105/0416 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 15, 2013
From: FUJITSU SEMICONDUCTOR LIMITED
To: FUJITSU SEMICONDUCTOR WIRELESS PRODUCTS, INC.
Reel/Frame 030793/0586 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 18, 2013
From: KAUFMAN, KRISTOPHER KEVIN; SIMMONS, JOHN WAYNE
To: FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 030637/0090 →