IP Library Granted Patent US 8,923,439
Granted Patent B1
US 8,923,439 · App. 13/912,905 · Granted Dec 30, 2014

Complementary signal mixing

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Quick Facts
Patent No.
US 8,923,439
App. No.
13/912,905
Granted
Dec 30, 2014
Kind
B1
Abstract

A method of performing complementary mixing may include performing an exclusive OR (XOR) function with respect to an I-channel symbol based on an oscillator signal to produce an I-channel output signal with bits that alternate between the I-channel symbol and a complement of the I-channel symbol in response to the oscillator signal rising and falling. The method may also include performing the XOR function with respect to a Q-channel symbol based on the oscillator signal to produce a Q-channel output signal with bits that alternate between the Q-channel symbol and a complement of the Q-channel symbol in response to the oscillator signal. Further, the method may include combining the I-channel output signal and the Q-channel output signal based on adding operations performed with respect to an I-channel extra bit signal, a Q-channel extra bit signal, the I-channel output signal, and the Q-channel output signal to generate a complementary mixed signal.

Claims (81)

1. A system configured to perform complementary signal mixing, the system comprising:

a complement generation module configured to:

receive an oscillator signal and a digital baseband I-channel signal that includes an I-channel symbol, the plurality of I-channel gates configured to perform an exclusive OR (XOR) function with respect to the I-channel symbol and the oscillator signal such that bits of an I-channel output signal that is based on an output of the plurality of I-channel logic gates alternate between the I-channel symbol and a complement of the I-channel symbol in response to the oscillator signal rising and falling;

receive the oscillator signal and a digital baseband Q-channel signal that includes a Q-channel symbol, the plurality of Q-channel gates configured to perform the XOR function with respect to the Q-channel symbol and the oscillator signal such that bits of a Q-channel output signal that is based on an output of the plurality of Q-channel logic gates alternate between the Q-channel symbol and a complement of the Q-channel symbol in response to the oscillator signal rising and falling; and

a combining module configured to combine the I-channel output signal and the Q-channel output signal based on adding operations performed with respect to an I-channel extra bit signal, a Q-channel extra bit signal, the I-channel output signal, and the Q-channel output signal to generate a complementary mixed signal having a frequency based on a clock frequency of the oscillator signal and including information included in the I-channel symbol and the Q-channel symbol.

2. The system of claim 1 , wherein the complement generation module comprises a phase-adjusting module configured to:

receive an intermediate I-channel signal that is based on the output of the plurality of I-channel gates;

receive an intermediate Q-channel signal that is based on the output of the plurality of Q-channel gates; and

adjust an I-channel phase of the intermediate I-channel signal with respect to a Q-channel phase of the intermediate Q-channel signal to generate the I-channel output signal and the Q-channel output signal such that the I-channel output signal and Q-channel output signal are substantially 90 degrees out of phase with each other.

3. The system of claim 2 , wherein the phase-adjusting module comprises:

an I-channel delay module configured to delay the intermediate I-channel signal by substantially one-half of a clock period of the oscillator signal to generate the I-channel output signal; and

a Q-channel delay module configured to delay the intermediate Q-channel signal by substantially one-fourth of the clock period to generate the Q-channel output signal, or wherein:

the I-channel delay module is configured to delay the intermediate I-channel signal by substantially one-fourth of the clock period to generate the I-channel output signal; and

the Q-channel delay module is configured to delay the intermediate Q-channel signal by substantially one-half of the clock period to generate the Q-channel output signal.

4. The system of claim 2 , wherein the phase-adjusting module is configured to:

delay the intermediate I-channel signal with respect to the intermediate Q-channel signal by substantially one-fourth of a clock period of the oscillator signal; or

delay the intermediate Q-channel signal with respect to the intermediate I-channel signal by substantially one-fourth of the clock period.

5. The system of claim 1 , wherein:

the complement generation module is further configured to:

combine the I-channel extra bit signal with the I-channel output signal to generate an extended I-channel output signal, a least significant bit of the I-channel output signal being based on the I-channel extra bit signal; and

combine the Q-channel extra bit signal with the Q-channel output signal to generate an extended Q-channel output signal, a least significant bit of the Q-channel output signal being based on the Q-channel extra bit signal; and

the combining module is configured to:

add the I-channel extra bit signal, the extended I-channel output signal, and the extended Q-channel output signal together to generate an adder output signal; and

add the Q-channel extra bit signal with the adder output signal during a digital-to-analog conversion of the adder output signal to generate the complementary mixed signal; or

add the Q-channel extra bit signal, the extended I-channel output signal, and the extended Q-channel output signal together to generate the adder output signal; and

add the I-channel extra bit signal with the adder output signal during the digital-to-analog conversion of the adder output signal to generate the complementary mixed signal.

6. The system of claim 5 , wherein:

the combining module is configured to remove a least significant bit of the sum of the I-channel extra bit signal, the extended I-channel output signal, and the extended Q-channel output signal to generate the adder output signal; or

the combining module is configured to remove a least significant bit of the sum of the Q-channel extra bit signal, the extended I-channel output signal, and the extended Q-channel output signal to generate the adder output signal.

7. The system of claim 1 , wherein the complement generation module is further configured to:

receive the oscillator signal and an I-channel extra bit control signal and is configured to perform the XOR function with respect to the oscillator signal and the I-channel extra bit control signal to generate the I-channel extra bit signal such that the I-channel extra bit signal alternates between “LOW” and “HIGH” in response to the oscillator signal rising and falling; and

receive the oscillator signal and a Q-channel extra bit control signal and is configured to perform the XOR function with respect to the oscillator signal and the Q-channel extra bit control signal to generate the Q-channel extra bit signal such that the Q-channel extra bit signal alternates between “LOW” and “HIGH” in response to the oscillator signal rising and falling.

8. The system of claim 1 , wherein:

the complement generation module includes an I-channel logic gate corresponding to a most significant bit of the I-channel symbol configured to receive a two's complement control signal to adjust for the I-channel symbol having a two's complement format or an unsigned binary code format; and

the complement generation module includes a Q-channel logic gate corresponding to a most significant bit of the Q-channel symbol configured to receive the two's complement control signal to adjust for the Q-channel symbol having the two's complement format or the unsigned binary code format.

9. The system of claim 1 , wherein the combining module includes:

an adding module configured to add the I-channel extra bit signal, the Q-channel extra bit signal, the I-channel output signal, and the Q-channel output signal together to generate an adder output signal; and

a summing digital-to-analog converter configured to perform an adding operation with respect to the adder output signal during a digital-to-analog conversion of the adder output signal to generate the complementary mixed signal.

10. The system of claim 1 , wherein the combining module includes:

a first summing digital-to-analog converter configured to perform an adding operation with respect to the I-channel extra bit signal and the I-channel output signal during a digital-to-analog conversion of the I-channel output signal to generate a modulated I-channel signal;

a second summing digital-to-analog converter configured to perform an adding operation with respect to the Q-channel extra bit signal and the Q-channel output signal during a digital-to-analog conversion of the Q-channel output signal to generate a modulated Q-channel signal; and

a signal mixer configured to combine the modulated I-channel signal with the modulated Q-channel signal to generate the complementary mixed signal.

11. A method of performing complementary signal mixing, the method comprising:

performing an exclusive OR (XOR) function with respect to an I-channel symbol based on an oscillator signal to produce an I-channel output signal with bits that alternate between the I-channel symbol and a complement of the I-channel symbol in response to the oscillator signal rising and falling;

performing the XOR function with respect to a Q-channel symbol based on the oscillator signal to produce a Q-channel output signal with bits that alternate between the Q-channel symbol and a complement of the Q-channel symbol in response to the oscillator signal rising and falling; and

combining the I-channel output signal and the Q-channel output signal based on adding operations performed with respect to an I-channel extra bit signal, a Q-channel extra bit signal, the I-channel output signal, and the Q-channel output signal to generate a complementary mixed signal having a frequency based on a clock frequency of the oscillator signal and including information included in the I-channel symbol and the Q-channel symbol.

12. The method of claim 11 , further comprising:

generating an intermediate I-channel signal based on performing the XOR function with respect to the I-channel symbol;

generating an intermediate Q-channel signal based on performing the XOR function with respect to the Q-channel symbol; and

adjusting an I-channel phase of the intermediate I-channel signal with respect to a Q-channel phase of the intermediate Q-channel signal to generate the I-channel output signal and the Q-channel output signal such that the I-channel output signal and Q-channel output signal are substantially 90 degrees out of phase with each other.

13. The method of claim 12 , further comprising:

delaying the intermediate I-channel signal by substantially one-half of a clock period of the oscillator signal to generate the I-channel output signal; and

delaying the intermediate Q-channel signal by substantially one-fourth of the clock period to generate the Q-channel output signal, or;

delaying the intermediate I-channel signal by substantially one-fourth of the clock period to generate the I-channel output signal; and

delaying the intermediate Q-channel signal by substantially one-half of the clock period to generate the Q-channel output signal.

14. The method of claim 12 , further comprising:

delaying the intermediate I-channel signal with respect to the intermediate Q-channel signal by substantially one-fourth of a clock period of the oscillator signal; or

delaying the intermediate Q-channel signal with respect to the intermediate I-channel signal by substantially one-fourth of the clock period.

15. The method of claim 11 , further comprising:

combining the I-channel extra bit signal with the I-channel output signal to generate an extended I-channel output signal, a least significant bit of the I-channel output signal being based on the I-channel extra bit signal; and

combining the Q-channel extra bit signal with the Q-channel output signal to generate an extended Q-channel output signal, a least significant bit of the Q-channel output signal being based on the Q-channel extra bit signal;

adding the I-channel extra bit signal, the extended I-channel output signal, and the extended Q-channel output signal together to generate an adder output signal; and

adding the Q-channel extra bit signal with the adder output signal during a digital-to-analog conversion of the adder output signal to generate the complementary mixed signal, or:

adding the Q-channel extra bit signal, the extended I-channel output signal, and the extended Q-channel output signal together to generate the adder output signal; and

adding the I-channel extra bit signal with the adder output signal during the digital-to-analog conversion of the adder output signal to generate the complementary mixed signal.

16. The method of claim 15 , further comprising:

removing a least significant bit of the sum of the I-channel extra bit signal, the extended I-channel output signal, and the extended Q-channel output signal to generate the adder output signal; or

removing a least significant bit of the sum of the Q-channel extra bit signal, the extended I-channel output signal, and the extended Q-channel output signal to generate the adder output signal.

17. The method of claim 11 , further comprising:

receiving the oscillator signal and an I-channel extra bit control signal and performing the XOR function with respect to the oscillator signal and the I-channel extra bit control signal to generate the I-channel extra bit signal such that the I-channel extra bit signal alternates between “LOW” and “HIGH” in response to the oscillator signal rising and falling; and

receiving the oscillator signal and a Q-channel extra bit control signal and performing the XOR function with respect to the oscillator signal and the Q-channel extra bit control signal to generate the Q-channel extra bit signal such that the Q-channel extra bit signal alternates between “LOW” and “HIGH” in response to the oscillator signal rising and falling.

18. The method of claim 11 , further comprising:

adjusting for the I-channel symbol having a two's complement format or an unsigned binary code format; and

adjusting for the Q-channel symbol having the two's complement format or the unsigned binary code format.

19. The method of claim 11 , further comprising:

adding the I-channel extra bit signal, the Q-channel extra bit signal, the I-channel output signal, and the Q-channel output signal together to generate an adder output signal; and

performing an adding operation with respect to the adder output signal during a digital-to-analog conversion of the adder output signal to generate the complementary mixed signal.

20. The method of claim 11 , further comprising:

performing a first adding operation with respect to the I-channel extra bit signal and the I-channel output signal during a digital-to-analog conversion of the I-channel output bit signal to generate a modulated I-channel signal;

performing a second adding operation with respect to the Q-channel extra bit signal and the Q-channel output signal during a digital-to-analog conversion of the Q-channel output signal to generate a modulated Q-channel signal; and

combining the modulated I-channel signal with the modulated Q-channel signal to generate the complementary mixed signal.

Assignments (4)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 28, 2021
From: INTEL IP CORPORATION
To: INTEL CORPORATION
Reel/Frame 056701/0807 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 28, 2013
From: FUJITSU SEMICONDUCTOR WIRELESS PRODUCTS, INC.
To: INTEL IP CORPORATION
Reel/Frame 031105/0416 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 15, 2013
From: FUJITSU SEMICONDUCTOR LIMITED
To: FUJITSU SEMICONDUCTOR WIRELESS PRODUCTS, INC.
Reel/Frame 030793/0586 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 7, 2013
From: YU, CHUANZHAO; KIRSCHENMANN, MARK
To: FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 030570/0915 →