Memory devices and memory operational methods including single erase operation of conductive bridge memory cells
Memory devices and memory operational methods are described. One example memory system includes a common conductor and a plurality of memory cells coupled with the common conductor. The memory system additionally includes access circuitry configured to provide different ones of the memory cells into one of a plurality of different memory states at a plurality of different moments in time between first and second moments in time. The access circuitry is further configured to maintain the common conductor at a voltage potential, which corresponds to the one memory state, between the first and second moments in time to provide the memory cells into the one memory state.
1. A memory device comprising:
a plurality of conductive bridge memory cells arranged in an array, the array comprising X banks each comprising Y tiles each comprising Z sub-tiles, wherein each of the Z sub-tiles comprises N of the conductive bridge memory cells and N>1;
Z common conductors each associated with one of the Z sub-tiles and the N conductive bridge memory cells of the one of the Z sub-tiles;
circuitry located at least partially with the array to write and read a memory state of the conductive bridge memory cells located in a page of the memory cells which are located across a plurality of the Z sub-tiles, wherein the page of the memory cells comprises less than the N conductive bridge memory cells; and
wherein the circuitry is configured to erase the N conductive bridge memory cells which are associated with one of the Z common conductors in a single erase operation.
2. The device of claim 1 wherein the circuitry is configured to erase the N conductive bridge memory cells which are associated with another of the Z common conductors in the single erase operation.
3. The device of claim 1 wherein the conductive bridge memory cells individually have a memory element which has different electrical resistances corresponding to a plurality of different memory states of the individual conductive bridge memory cell.
4. The device of claim 1 wherein the conductive bridge memory cells in an erased memory state individually have at least one conductive structure providing the individual conductive bridge memory cell with a reduced electrical resistance compared with another of the memory states.
5. The device of claim 1 wherein the circuitry is configured to erase different ones of the N conductive bridge memory cells which are associated with the one of the Z common conductors at a plurality of different moments in time between first and second moments in time.
6. The device of claim 5 wherein the circuitry is configured to maintain the one of the Z common conductors at a voltage potential utilized for an erase operation between the first and second moments in time to erase the N conductive bridge memory cells which are associated with one of the Z common conductors.
7. The device of claim 6 wherein the circuitry is configured to erase the different ones of the N conductive bridge memory cells using different word lines.
8. The device of claim 1 wherein the circuitry comprises a plurality of access circuits which are individually configured to write, read and erase the N conductive bridge memory cells of a respective one of the Z sub-tiles.
9. The device of claim 8 wherein plural ones of the access circuits are configured to simultaneously write and read the memory state of the conductive bridge memory cells located in the page of the memory cells and in respective ones of the Z sub-tiles.
10. The device of claim 8 wherein plural ones of the access circuits are configured to simultaneously erase the N conductive bridge memory cells of respective ones of the Z sub-tiles during the single erase operation.
11. A memory device comprising:
a plurality of conductive bridge memory cells arranged in an array, the array comprising X banks each comprising Y tiles each comprising Z sub-tiles, wherein each of the Z sub-tiles comprises N of the conductive bridge memory cells, wherein the conductive bridge memory cells individually have different electrical resistances in different ones of a plurality of memory states;
Z common conductors each associated with one of the Z sub-tiles and the N conductive bridge memory cells of the one of the Z sub-tiles;
a plurality of access circuits located at least partially with the array and individually configured to write and read the memory states of the conductive bridge memory cells located in different respective ones of the Y tiles;
wherein the access circuits write and read a page of the memory cells which are located across a plurality of the Z sub-tiles, wherein the page of the memory cells comprises less than the N conductive bridge memory cells, and wherein the access circuits simultaneously write and read the conductive bridge memory cells of the page in different ones of the Y tiles to write and read the page of the memory cells;
wherein the access circuits simultaneously erase a plurality of the conductive bridge memory cells of a plurality of the Z common conductors in a single erase operation; and
wherein one of the access circuits erases different ones of the N conductive bridge memory cells which are associated with one of the Z common conductors at a plurality of different moments in time between first and second moments in time and the one access circuit maintains the one of the Z common conductors at a voltage potential utilized for an erase operation between the first and second moments in time.
12. A method of operating a memory comprising an array of a plurality of conductive bridge memory cells, the array comprising X banks each comprising Y tiles each comprising Z sub-tiles, wherein each of the Z sub-tiles comprises a common conductor associated with N of the conductive bridge memory cells and N>1, the method comprising:
reading and writing a memory state of the conductive bridge memory cells located in a page of the memory cells which are located across a plurality of the Z sub-tiles, wherein the page of the memory cells comprises less than the N conductive bridge memory cells; and
erasing the N conductive bridge memory cells of one of the Z sub-tiles in a single erase operation.
13. The method of claim 12 wherein the erasing comprises erasing the N conductive bridge memory cells which are associated with others of the Z common conductors in the single erase operation.
14. The method of claim 12 wherein the erasing comprises changing electrical resistances of the N conductive bridge memory cells.
15. The method of claim 12 wherein the erasing comprises forming at least one conductive structure within an individual ones of the N conductive bridge memory cells to reduce the electrical resistance of the individual conductive bridge memory cell compared with another of the memory states.
16. The method of claim 12 wherein the erasing comprises erasing different ones of the N conductive bridge memory cells of the one of the Z sub-tiles at a plurality of different moments in time between first and second moments in time.
17. The method of claim 16 wherein the erasing comprises maintaining the common conductor of the one of the Z sub-tiles at a voltage potential utilized for an erase operation between the first and second moments in time.
18. The method of claim 17 wherein the erasing comprises erasing the different ones of the N conductive bridge memory cells using different word lines.
19. The method of claim 12 wherein the reading and writing comprise reading and writing the conductive bridge memory cells located in the page of the memory cells which are located across the plural Z sub-tiles simultaneously using a plurality of access circuits which are associated with respective ones of the Z sub-tiles.
20. The method of claim 12 wherein the erasing comprises simultaneously erasing the conductive bridge memory cells of plural ones of the Z sub-tiles using a plurality of access circuits which are associated with respective ones of the Z sub-tiles.