Programming an array of resistance random access memory cells using unipolar pulses
View Patent ↗Subject matter disclosed herein relates to a memory device, and more particularly to programming a non-volatile memory device.
1. A method of programming information to a non-volatile memory cell, comprising:
providing a write command for programming the information to the non-volatile memory cell;
driving the non-volatile memory cell to an unstable state in response to the write command by applying to the non-volatile memory cell a first portion of an electrical programming signal; and
returning the non-volatile memory cell from the unstable state to a desired stable state by applying to the non-volatile memory cell a second portion of the electrical programming signal, wherein a plot of magnitude over time of the second portion of the electrical programming signal has a shape different from that of the first portion of the electrical programming signal.
2. The method of claim 1 , wherein driving the non-volatile memory cell to the unstable state comprises applying to the non-volatile memory cell the first portion of the electrical programming signal at a sufficiently high voltage to drive the non-volatile memory cell to a high voltage unstable state.
3. The method of claim 2 , wherein the electrical programming signal comprises a varying voltage, wherein a magnitude of the voltage has a peak magnitude in the first portion, the peak magnitude sufficient to drive the non-volatile memory cell to the high-voltage unstable state.
4. The method of claim 1 , wherein the non-volatile memory cell comprises a resistance random access memory (RRAM) cell, and the write command comprises a command to transition the resistance random access memory cell between a set state and a reset state.
5. The method of claim 4 , wherein the electrical programming signal comprises a voltage signal for transitioning the non-volatile memory cell from the set state to the reset state.
6. The method of claim 5 , wherein the voltage signal applied to the non-volatile memory cell in the unstable state comprises a voltage greater than a threshold switching voltage of the non-volatile memory cell in the reset state.
7. The method of claim 1 , wherein the electrical programming signal comprises a decreasing electrical programming signal during the second portion.
8. The method of claim 7 , wherein the decreasing electrical programming signal comprises a decaying resistor-capacitor (RC) voltage.
9. The method of claim 1 , further comprising verifying a proper programming of the non-volatile memory cell subsequent to returning the non-volatile memory cell to the desired stable state.
10. The method of claim 1 , wherein the non-volatile memory cell is returned to the desired stable state during applying the second portion of the electrical programming signal.
11. A memory device comprising:
a memory array comprising a non-volatile memory cell; and
a memory controller configured to program information to the non-volatile memory cell of the memory array by:
receiving a write command to program the information to the non-volatile memory cell;
driving the non-volatile memory cell to an unstable state in response to the write command by applying to the non-volatile memory cell a first portion of an electrical programming signal; and
returning the non-volatile memory cell from the unstable state to a desired stable state by applying to the non-volatile memory cell a second portion of the electrical programming signal, wherein a plot of magnitude over time of the second portion of the electrical programming signal has a shape different from that of the first portion of the electrical programming signal.
12. The memory device of claim 11 , wherein the memory array comprises a resistance random access memory (RRAM), and the write command comprises a command to transition the non-volatile memory cell between a set state and a reset state.
13. The memory device of claim 11 , wherein driving the non-volatile memory cell to the unstable state comprises applying to the non-volatile memory cell the first portion of the electrical programming signal at a sufficiently high voltage to drive the non-volatile memory cell to a high voltage unstable state.
14. The memory device of claim 13 , wherein the electrical programming signal comprises a varying voltage, wherein a magnitude of the voltage has a peak magnitude in the first portion, the peak magnitude sufficient to drive the non-volatile memory cell to the high voltage unstable state.
15. The memory device of claim 11 , wherein the electrical programming signal comprises a decreasing electrical programming signal during the second portion.
16. The memory device of claim 15 , wherein the decreasing electrical programming signal comprises a decaying resistor-capacitor (RC) voltage.
17. The memory device of claim 11 , wherein the memory controller comprises a drive circuit having at least a variable current source, an operational amplifier and a shunt resistor for driving the non-volatile memory cell to an unstable state.
18. The memory device of claim 11 , wherein the memory controller comprises a drive circuit having a capacitor and a parallel variable resistor for driving the non-volatile memory cell to an unstable state.
19. A system, comprising
a memory array comprising a non-volatile memory cell;
a processor configured to initiate a write command to program information to the non-volatile memory cell of the memory array; and
a memory controller configured to program the information to the non-volatile memory cell by:
receiving the write command to program the information to the non-volatile memory cell;
driving the non-volatile memory cell to an unstable state in response to the write command by applying to the non-volatile memory cell a first portion of an electrical programming signal; and
returning the non-volatile memory cell from the unstable state to a desired stable state by applying to the non-volatile memory cell a second portion of the electrical programming signal, wherein a plot of magnitude over time of the second portion of the electrical programming signal has a shape different from that of the first portion of the electrical programming signal.
20. The system of claim 19 , wherein driving the non-volatile memory cell to the unstable state comprises applying to the non-volatile memory cell the first portion of the electrical programming signal at a sufficiently high voltage to drive the non-volatile memory cell to a high voltage unstable state.
21. The system of claim 19 , wherein the second portion of the electrical programming signal comprises a decaying resistor-capacitor (RC) voltage.