Phased-array receiver for mm-wave applications

1. A circuit for providing a signal gain, comprising:

a first stage comprising a first set of variable gain transconductors arranged for receiving an input voltage signal and for performing phase-shifting of the input voltage signal, thereby producing an intermediate current signal, and

a second stage comprising a second set of transconductors and a plurality of capacitors arranged for receiving the intermediate current signal and for providing an output signal to a combiner,

wherein the first stage and the second stage together form a filter, and wherein the first set of variable gain transconductors and at least one of the transconductors of the second set are configured to be selectively activated, such that a ratio of activated variable gain transconductors of the first set and at least one activated transconductor of the second set defines a controllable signal gain of the circuit.

2. The circuit of claim 1 , wherein the first stage comprises multiple first sets of variable gain transconductors arranged for performing beamforming, each first set receiving a different input signal and each having outputs connected in parallel, which in combination yield the intermediate current signal.

3. The circuit of claim 1 , wherein the cut-off frequency and quality factor of the circuit are determined by the second set of transconductors and the plurality of capacitors.

4. The circuit of claim 1 , wherein an overall transfer function of the circuit takes into account a parasitic capacitance due to on-chip interconnects, thereby reducing a need for using buffering to compensate for signal losses due to the parasitic capacitance.

5. A circuit for providing a signal gain, comprising:

a first stage comprising a plurality of first sets of variable gain transconductors, each arranged for receiving a respective input voltage signal and for performing phase-shifting of the respective input voltage signal,

combining means for combining outputs signals of the first stage, thereby producing an intermediate current signal, and

a second stage comprising a second set of transconductors and a plurality of capacitors arranged for receiving the intermediate current signal and for providing an output signal to a combiner,

wherein the first stage and the second stage together form a filter, and wherein the plurality of first sets of variable gain transconductors and at least one of the transconductors of the second set are configured to be selectively activated, such that a ratio of activated variable gain transconductors of the plurality of first sets and at least one activated transconductor of the second set defines a controllable signal gain of the circuit.

6. The circuit of claim 5 , wherein the first stage comprises multiple first sets of variable gain transconductors arranged for performing beamforming, each first set receiving a different input signal and each having outputs connected in parallel, which in combination yield the intermediate current signal.

7. The circuit of claim 5 , wherein the cut-off frequency and quality factor of the circuit are determined by the second set of transconductors and the plurality of capacitors.

8. The circuit of claim 5 , wherein an overall transfer function of the circuit takes into account a parasitic capacitance due to on-chip interconnects, thereby reducing a need for using buffering to compensate for signal losses due to the parasitic capacitance.

9. A wireless phased-array receiver, comprising:

at least two front-end circuits each comprising an antenna for receiving an input signal, a low-noise amplifier for amplifying the received input signal, and a down-converter for down-converting the amplified signal, each front-end circuit thereby providing an analogue baseband signal,

at least one circuit arranged for receiving a plurality of analogue baseband signals provided by the at least two front-end circuits and performing phase-shifting and filtering of the plurality of analogue baseband signals, wherein an overall transfer function of the at least one circuit takes into account a parasitic capacitance due to on-chip interconnects, thereby reducing a need for using buffering to compensate for signal losses due to the parasitic capacitance, and

an amplifier for amplifying one or more phase-shifted and filtered analogue baseband signals.

10. The wireless phased-array receiver of claim 9 , wherein each of the at least one circuits comprises:

a first stage comprising a first set of variable gain transconductors arranged for receiving an analogue baseband signal and for performing phase-shifting of the analogue baseband signal, thereby producing an intermediate signal, and

a second stage comprising a second set of transconductors and a plurality of capacitors arranged for receiving the intermediate signal and for providing a phase-shifted and filtered analogue baseband signal.

11. The wireless phased-array receiver of claim 9 , wherein each of the at least one circuits comprises:

a first stage comprising a plurality of first sets of variable gain transconductors, each arranged for receiving an analogue baseband signal and for performing phase-shifting of the analogue baseband signal,

combining means for combining outputs signals of the first stage, thereby producing an intermediate signal, and

a second stage comprising a second set of transconductors and a plurality of capacitors arranged for receiving the intermediate signal and for providing a phase-shifted and filtered analogue baseband signal.

12. The wireless phased-array receiver of claim 9 , further comprising a combiner configured to combine the one or more phase-shifted and filtered analogue baseband signals.

13. The wireless phased-array receiver of claim 12 , wherein the combiner comprises an RC filter.

14. The wireless phased-array receiver of claim 9 , configured to combine multiple analogue baseband signals after performing the phase-shifting and before performing the filtering.

15. The wireless phased-array receiver of claim 9 , wherein the wireless phased-array receiver is implemented in 40 nanometer complementary metal-oxide-semiconductor (CMOS) technology.

16. The wireless phased-array receiver of claim 9 , wherein the wireless phased-array receiver is a component of a communication network.