IP Library Granted Patent US 8,952,381
Granted Patent B2
US 8,952,381 · App. 13/920,417 · Granted Feb 10, 2015

Semiconductor device

Inventor: Shunpei Yamazaki (Setagaya, JP)
Assignee: Semiconductor Energy Laboratory Co., Ltd.
H01L29/24H01L29/7869H01L29/66742H01L27/14632H01L27/14687
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Quick Facts
Patent No.
US 8,952,381
App. No.
13/920,417
Granted
Feb 10, 2015
Kind
B2
Abstract

High field-effect mobility is provided for a semiconductor device including an oxide semiconductor. Further, a highly reliable semiconductor device including the transistor is provided. In a transistor in which a stack of oxide semiconductor layers is provided over a gate electrode layer with a gate insulating layer provided therebetween, an oxide semiconductor layer functioning as a current path (channel) of the transistor and containing an n-type impurity is sandwiched between oxide semiconductor layers having lower conductivity than the oxide semiconductor layer. In the oxide semiconductor layer functioning as the channel, a region on the gate insulating layer side contains the n-type impurity at a higher concentration than a region on the back channel side. With such a structure, the channel can be separated from the interface between the oxide semiconductor stack and the insulating layer in contact with the oxide semiconductor stack, so that a buried channel can be formed.

Claims (46)

1. A semiconductor device comprising:

a gate electrode layer;

a first oxide semiconductor layer;

a gate insulating layer between the gate electrode layer and the first oxide semiconductor layer;

a second oxide semiconductor layer electrically connected to the first oxide semiconductor layer, the second oxide semiconductor layer comprising:

a first region; and

a second region;

a third oxide semiconductor layer electrically connected to the second oxide semiconductor layer; and

a source electrode layer and a drain electrode layer electrically connected to the third oxide semiconductor layer,

wherein the third oxide semiconductor layer covers a side surface of the second oxide semiconductor layer,

wherein the second oxide semiconductor layer contains an n-type impurity,

wherein the first region is closer to the first oxide semiconductor layer than the second region, and

wherein the first region contains the n-type impurity at a higher concentration than the second region.

2. The semiconductor device according to claim 1 ,

wherein the semiconductor device further comprises an insulating layer in contact with the source electrode layer and the drain electrode layer.

3. The semiconductor device according to claim 1 ,

wherein each of the first oxide semiconductor layer, the second oxide semiconductor layer, and the third oxide semiconductor layer comprises indium.

4. The semiconductor device according to claim 1 ,

wherein the first oxide semiconductor layer and the third oxide semiconductor layer are i-type oxide semiconductor layers.

5. The semiconductor device according to claim 1 ,

wherein metal elements included in the first oxide semiconductor layer are included in the second oxide semiconductor layer and the third oxide semiconductor layer.

6. A semiconductor device comprising:

a gate electrode layer;

a gate insulating layer over the gate electrode layer;

a first oxide semiconductor layer over the gate insulating layer;

a second oxide semiconductor layer over the first oxide semiconductor layer, the second oxide semiconductor layer comprising:

a first region; and

a second region;

a third oxide semiconductor layer over the second oxide semiconductor layer; and

a source electrode layer and a drain electrode layer electrically connected to the third oxide semiconductor layer,

wherein the third oxide semiconductor layer covers a side surface of the second oxide semiconductor layer,

wherein the second oxide semiconductor layer contains an n-type impurity,

wherein the first region is closer to the first oxide semiconductor layer than the second region, and

wherein the first region contains the n-type impurity at a higher concentration than the second region.

7. The semiconductor device according to claim 6 ,

wherein the source electrode layer and the drain electrode layer are over the third oxide semiconductor layer.

8. The semiconductor device according to claim 6 ,

wherein the semiconductor device further comprises an insulating layer over the third oxide semiconductor layer.

9. The semiconductor device according to claim 6 ,

wherein each of the first oxide semiconductor layer, the second oxide semiconductor layer, and the third oxide semiconductor layer comprises indium.

10. The semiconductor device according to claim 6 ,

wherein the third oxide semiconductor layer covers the first oxide semiconductor layer and the second oxide semiconductor layer.

11. The semiconductor device according to claim 6 ,

wherein the first oxide semiconductor layer and the third oxide semiconductor layer are i-type oxide semiconductor layers.

12. The semiconductor device according to claim 6 ,

wherein metal elements included in the first oxide semiconductor layer are included in the second oxide semiconductor layer and the third oxide semiconductor layer.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 18, 2013
From: YAMAZAKI, SHUNPEI
To: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Reel/Frame 030635/0160 →
Priority Claims (1)
JP 2012-147178 · Jun 29, 2012 · national
Continuity (1)
Related Publication 20140001465A1 · Jan 2, 2014