IP Library Granted Patent US 9,398,700
Granted Patent B2
US 9,398,700 · App. 13/924,002 · Granted Jul 19, 2016

Method of forming a reliable microelectronic assembly

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 9,398,700
App. No.
13/924,002
Granted
Jul 19, 2016
Kind
B2
Abstract

Microelectronic assemblies and methods for making the same are disclosed herein. In one embodiment, a method of forming a microelectronic assembly comprises assembling first and second components to have first major surfaces of the first and second components facing one another and spaced apart from one another by a predetermined spacing, the first component having first and second oppositely-facing major surfaces, a first thickness extending in a first direction between the first and second major surfaces, and a plurality of first metal connection elements at the first major surface, the second component having a plurality of second metal connection elements at the first major surface of the second component; and plating a plurality of metal connector regions each connecting and extending continuously between a respective first connection element and a corresponding second connection element opposite the respective first connection element in the first direction.

Claims (41)

1. A method of forming a microelectronic assembly, comprising:

assembling first and second components to have first major surfaces of the first and second components facing one another and spaced apart from one another by a predetermined spacing, the first component having first and second oppositely-facing major surfaces, a first thickness extending in a first direction between the first and second major surfaces, and a plurality of first metal connection elements at the first major surface, the second component having a plurality of second metal connection elements at the first major surface of the second component;

prior to assembling the first and second components, forming the first metal connection elements by a method comprising: forming at least one of first metal vias extending in the first direction of the first thickness between first and second major surfaces of the first component, or first metal pads at the first major surface of the first component, forming a first seed layer overlying the first major surface of the first component and electrically connected to the at least one of the first metal vias or first metal pads, and plating first plated metal regions above the at least one of first metal vias or first metal pads, the first plated metal regions extending in the first direction at least above the first major surface of the first component, the first seed layer electrically connecting each first plated metal region to a corresponding first metal via or first metal pad;

plating a plurality of metal connector regions each connecting and extending continuously in the first direction between a respective first surface of the first plated metal region and a corresponding second surface of the second metal connection element opposite the respective first plated metal region, each metal connector region plated between corresponding exposed portions of the first and second surfaces; and

removing portions of the first seed layer to electrically separate adjacent first metal connection elements.

2. The method of claim 1 , wherein prior to assembling the first and second components, further comprising:

separately forming the second metal connection elements by a method comprising:

forming at least one of second metal vias extending in a direction of thickness of the second component between first and second major surfaces of the second component, or second metal pads at the first major surface of the second component; and

plating second plated metal regions above the at least one of second metal vias or second metal pads, the second plated metal regions extending at least above the first major surface of the second component,

wherein each plated metal connector region is connecting and extending continuously in the first direction between a respective first surface of the first plated metal region and a corresponding second surface of the second plated metal region opposite the respective first plated metal region.

3. The method of claim 2 , wherein forming the second metal connection elements further comprises:

forming a second seed layer overlying the first major surface of the second component and electrically connected to the at least one of the second metal vias or second metal pads, wherein the second seed layer electrically connects each second plated metal region to a corresponding second metal via or second metal pad.

4. The method of claim 3 , wherein plating the first and second plated metal regions further comprises:

separately forming patterned dielectric layers overlying each of the first and second layers, the patterned dielectric layers having openings which expose portions of the first and second seed layers that overlie, respectively, each first metal via or first metal pad, and each second metal via or second metal pad; and

forming the first and second plated metal regions in the openings.

5. The method of claim 4 , wherein prior to assembling the first and second components, further comprising:

removing the patterned dielectric layers after formation of the first and second plated metal regions; and

separately forming second dielectric layers overlying, respectively, the first and second seed layers and sidewall surfaces of the first and second plated metal regions, wherein the first and second surfaces of each first and second plated metal region are exposed.

6. The method of claim 5 , wherein after assembling the first and second components and plating of the metal connector regions, further comprising:

removing the second dielectric layers; and

removing portions of the second seed layers to electrically separate adjacent second metal connection elements.

7. The method of claim 6 , wherein prior to or after removing the second dielectric layers further comprising:

forming a plurality of barrier regions overlying the sidewalls of at least one of the metal connector regions, the first plated metal regions, or the second plated metal regions.

8. The method of claim 1 , wherein assembling the first and second components further comprises:

forming an element disposed between the first major surfaces of the first and second microelectronic elements, the element bonding the first and second components with one another, wherein the predetermined spacing includes a thickness of the element.

9. The method of claim 1 , wherein at least some corresponding first and second metal connection elements do not share a common axis.

10. The method of claim 1 , wherein at least some first and second surfaces of the first metal connection elements and the respective second metal connection elements connected thereto are not parallel to a common plane.

11. A method of forming a microelectronic assembly, comprising:

assembling first and second components to have first major surfaces of the first and second components facing one another and spaced apart from one another by a predetermined spacing, the first component having first and second oppositely-facing major surfaces, a first thickness extending in a first direction between the first and second major surfaces, and a plurality of first metal connection elements at the first major surface, the second component having a plurality of second metal connection elements at the first major surface of the second component;

prior to assembling the first and second components, forming the first metal connection elements by a method comprising: forming at least one of first metal vias extending in the first direction of the first thickness between first and second major surfaces of the first component, or first metal pads at the first major surface of the first component, and forming a first seed layer overlying the first major surface of the first component and electrically connected to the at least one of the first metal vias or first metal pads;

plating a plurality of metal connector regions each connecting and extending continuously between a respective first connection element and a corresponding second connection element opposite the respective first connection element in the first direction, each metal connector region plated between corresponding exposed portions of the first seed layer and the second metal connection elements; and

removing portions of the first seed layer to electrically separate adjacent first metal connection elements.

12. The method of claim 11 , wherein prior to assembling the first and second components, forming the second metal connection elements by a method comprising:

forming at least one of second metal vias extending in a direction of thickness of the second component between first and second major surfaces of the second component, or second metal pads at the first major surface of the second component; and

forming a second seed layer overlying the first major surface of the second component and electrically connected to the at least one of the second metal vias or second metal pads.

13. The method of claim 12 , wherein prior to assembling the first and second components, further comprising:

separately forming patterned dielectric layers overlying each of the first and second layers, the patterned dielectric layers exposing portions of the first and second seed layers that overlie, respectively, each first metal via or first metal pad, and each second metal via or second metal pad.

14. The method of claim 13 , further comprising:

removing portions of the second seed layers to electrically separate adjacent second metal connection elements.

15. The method of claim 14 , prior to or after removing portions of the first and second seed layers, further comprising:

forming a plurality of barrier regions overlying sidewalls of the metal connector regions.

Assignments (6)
CHANGE OF NAME Recorded Nov 24, 2025
From: INVENSAS LLC
To: ADEIA SEMICONDUCTOR TECHNOLOGIES LLC
Reel/Frame 073508/0661 →
CHANGE OF NAME Recorded Nov 24, 2025
From: INVENSAS CORPORATION
To: INVENSAS LLC
Reel/Frame 073689/0793 →
RELEASE OF SECURITY INTEREST Recorded Jun 11, 2020
From: ROYAL BANK OF CANADA
To: TESSERA, INC.; INVENSAS BONDING TECHNOLOGIES, INC. (F/K/A ZIPTRONIX, INC.); FOTONATION CORPORATION (F/K/A DIGITALOPTICS CORPORATION AND F/K/A DIGITALOPTICS CORPORATION MEMS); INVENSAS CORPORATION; TESSERA ADVANCED TECHNOLOGIES, INC; DTS, INC.; DTS LLC; PHORUS, INC.; IBIQUITY DIGITAL CORPORATION
Reel/Frame 052920/0001 →
SECURITY INTEREST Recorded Jun 1, 2020
From: ROVI SOLUTIONS CORPORATION; ROVI TECHNOLOGIES CORPORATION; ROVI GUIDES, INC.; TIVO SOLUTIONS INC.; VEVEO, INC.; INVENSAS CORPORATION; INVENSAS BONDING TECHNOLOGIES, INC.; TESSERA, INC.; TESSERA ADVANCED TECHNOLOGIES, INC.; DTS, INC.; PHORUS, INC.; IBIQUITY DIGITAL CORPORATION
To: BANK OF AMERICA, N.A.
Reel/Frame 053468/0001 →
SECURITY INTEREST Recorded Dec 2, 2016
From: INVENSAS CORPORATION; TESSERA, INC.; TESSERA ADVANCED TECHNOLOGIES, INC.; ZIPTRONIX, INC.; DIGITALOPTICS CORPORATION; DIGITALOPTICS CORPORATION MEMS; DTS, LLC; DTS, INC.; PHORUS, INC.; IBIQUITY DIGITAL CORPORATION
To: ROYAL BANK OF CANADA, AS COLLATERAL AGENT
Reel/Frame 040797/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 20, 2013
From: UZOH, CYPRIAN EMEKA; HABA, BELGACEM; WOYCHIK, CHARLES G.; NEWMAN, MICHAEL; CASKEY, TERRENCE
To: INVENSAS CORPORATION
Reel/Frame 031336/0011 →