Method for fabricating fin-shaped field-effect transistor

1. A method for fabricating fin-shaped field-effect transistor (FinFET), comprising:

providing a substrate;

forming a fin-shaped structure on the substrate;

forming a first gate structure on the fin-shaped structure;

forming a first epitaxial layer in the fin-shaped structure adjacent to the first gate structure;

forming an interlayer dielectric layer on the first gate structure and the first epitaxial layer;

forming an opening in the interlayer dielectric layer to expose the first epitaxial layer;

forming a silicon cap on the first epitaxial layer; and

forming a contact plug in the opening.

2. The method for fabricating FinFET of claim 1 , further comprising forming a shallow trench isolation (STI) on the substrate and around the fin-shaped structure before forming the first gate structure.

3. The method for fabricating FinFET of claim 2 , wherein the first gate structure comprises:

a polysilicon layer on the fin-shaped structure and the STI; and

a hard mask on the polysilicon layer.

4. The method for fabricating FinFET of claim 3 , further comprising:

forming the first gate structure on a first transistor region of the substrate and on the STI and a second gate structure on a second transistor region of the substrate and on the STI;

forming a first hard mask on the first gate structure and the second gate structure;

removing a portion of the first hard mask on the first transistor region to form a first spacer around the first gate structure and a first recess in the fin-shaped structure adjacent to the first gate structure;

forming a first epitaxial layer in the first recess;

forming a second hard mask on the first gate structure and the second gate structure;

removing the second hard mask on the second transistor region to form another first spacer around the second gate structure and a second recess in the fin-shaped structure adjacent to the second gate structure; and

forming a second epitaxial layer in the second recess.

5. The method for fabricating FinFET of claim 4 , wherein the first transistor region is a PMOS region and the second transistor region is a NMOS region.

6. The method for fabricating FinFET of claim 4 , wherein the first hard mask and the second hard mask is selected from a group consisting of SiC, SiON, SiN, SiCN, and SiBN.

7. The method for fabricating FinFET of claim 4 , wherein the first epitaxial layer comprises silicon germanium and the second epitaxial layer comprises silicon phosphorus.

8. The method for fabricating FinFET of claim 4 , further comprising removing the first spacer from the first gate structure and the second gate structure.

9. The method for fabricating FinFET of claim 4 , further comprising:

forming a second spacer around the first gate structure and the second gate structure;

forming an oxide seal on the second spacer, the first gate structure, and the second gate structure;

forming a source/drain region adjacent to the first gate structure and the second gate structure;

removing the oxide seal;

performing a replacement metal gate (RMG) process to form a metal gate in each of the first transistor region and the second transistor region;

forming a cap film on the metal gate;

forming the opening in the cap film and the interlayer dielectric layer to expose the first epitaxial layer and the second epitaxial layer;

forming the silicon cap on the first epitaxial layer and the second epitaxial layer;

forming a silicide layer on the first epitaxial layer and the second epitaxial layer; and

forming the contact plug in the opening.

10. The method for fabricating FinFET of claim 9 , further comprising using diluted hydrofluoric acid (DHF) for removing the oxide seal.

11. The method for fabricating FinFET of claim 9 , wherein the RMG process comprises:

removing the hard mask and polysilicon layer for forming a recess in each of the first gate structure and the second gate structure;

forming a high-k dielectric layer in the recess;

depositing a work function metal layer in the recess; and

planarizing the work function metal layer and the high-k dielectric layer for forming the metal gate in each of the first transistor region and the second transistor region.

12. The method for fabricating FinFET of claim 9 , wherein the cap film comprises oxide.

13. The method for fabricating FinFET of claim 9 , wherein the step of forming the contact plug further comprises:

forming a barrier layer in the opening;

depositing a metal layer to fill the opening; and

planarizing the metal layer and the barrier layer to form the contact plug in the opening.

14. The method for fabricating FinFET of claim 13 , wherein the metal layer comprises tungsten.