Method and apparatus providing pixel array having automatic light control pixels and image capture pixels
View Patent ↗A pixel array uses two sets of pixels to provide accurate exposure control. One set of pixels provide continuous output signals for automatic light control (ALC) as the other set integrates and captures an image. ALC pixels allow monitoring of multiple pixels of an array to obtain sample data indicating the amount of light reaching the array, while allowing the other pixels to provide proper image data. A small percentage of the pixels in an array is replaced with ALC pixels and the array has two reset lines for each row; one line controls the reset for the image capture pixels while the other line controls the reset for the ALC pixels. In the columns, at least one extra control signal is used for the sampling of the reset level for the ALC pixels, which happens later than the sampling of the reset level for the image capture pixels.
1. A pixel array comprising:
at least one row of pixels, each row comprising:
a first plurality of pixels, each comprising a photosensor, a charge storage region, a reset transistor for resetting said charge storage region, and a transfer transistor for selectively transferring charge from said photosensor to said charge storage region after an integration period and preventing transfer of charge from said photosensor to said charge collection region during said integration period; and
at least one pixel comprising a photosensor for providing charge to a charge storage region during an integration period, a reset transistor for resetting said charge storage region, and an always-activated transfer transistor for allowing transfer of charge from said photosensor to said charge storage region.
2. The pixel array of claim 1 , further comprising:
a first reset control line connected to operate the reset transistor of said plurality of pixels; and
a second control reset line connected to operate the reset transistor of said at least one pixel.
3. The pixel array of claim 2 , further comprising a control circuit for resetting said first reset control line at a different time than said second reset control line.
4. The pixel array of claim 1 , wherein said at least one pixel is used for automatic light control of said plurality of pixels.
5. The pixel array of claim 4 , wherein said pixel array is a color pixel array with said plurality of pixels and said at least one pixel being arranged in a Bayer pattern.
6. The pixel array of claim 5 , wherein a subset of pixels of one color of said Bayer pattern is used for automatic light control.
7. The pixel array of claim 6 , wherein said color is red.
8. The pixel array of claim 6 , wherein said subset of pixels is dispersed throughout the pixel array.
9. The pixel array of claim 1 , wherein said plurality of image capture pixels have a different integration period than said at least one automatic light control pixel.
10. An image processing system comprising:
a processor; and
an imager structure comprising:
at least one row of pixels, each row comprising:
a first plurality of pixels, each comprising a photosensor, a charge storage region, a reset transistor for resetting signal from said charge storage region, and a transfer transistor for selectively transferring charge from said photosensor to said charge storage region after an integration period and preventing transfer of charge from said photosensor to said charge collection region when not activated; and
at least one pixel comprising a photosensor for providing charge to a charge storage region during charge integration, a reset transistor for resetting said charge storage region, and an always-activated transfer transistor for allowing transfer of charge from said photosensor to said charge storage region.
11. The image processing system of claim 10 , wherein said system is a camera processor system.
12. A pixel array comprising:
at least one row of pixels, each row comprising:
a first plurality of pixels, each comprising a photosensor, a charge storage region, a reset transistor for resetting signal from said charge storage region, and a transfer transistor for selectively transferring charge from said photosensor to said charge storage region after an integration period and preventing transfer of charge from said photosensor to said charge collection region when not activated; and
at least one pixel comprising a photosensor for providing charge to a charge storage region during charge integration, a reset transistor for resetting said charge storage region, a transfer transistor for allowing transfer of charge from said photosensor to said charge storage region, a source follower transistor for converting charges stored at the charge storage region to the output voltage, the source follower transistor being powered by the supply voltage, and a row select transistor for switchably providing the output voltage to a column line, the at least one pixel being operated in a three-transistor mode.
13. The pixel array of claim 12 , wherein the at least one pixel is operated in a three-transistor mode by maintaining the transfer transistor in an activated state.