Immediate direct memory access descriptor-based write operation

1. A method comprising:

processing a direct memory access (DMA) descriptor in a DMA controller, the DMA descriptor including first data and second data;

storing the first data at an address identified by the second data,

wherein processing the DMA descriptor comprises:

determining, based on third data of the DMA descriptor, to identify the DMA descriptor as being associated with a first descriptor type; and

in response to the determination, reading the first data from a field of the DMA descriptor, the field being associated with a memory address and being associated with a second descriptor type.

2. The method of claim 1 , wherein processing the DMA descriptor comprises generating a write operation on a bus to communicate the first data and the address identified by the second data.

3. The method of claim 1 , wherein processing the DMA descriptor comprises performing a single write operation on a bus to store the second data in an input/output (I/O) location identified by the address.

4. The method of claim 1 , wherein processing the DMA descriptor comprises storing the first data in a memory of a peripheral device.

5. The method of claim 4 , wherein the peripheral device comprises the DMA controller or a device other than the DMA controller.

6. An apparatus comprising:

a system memory;

an input/output (I/O) memory; and

a direct memory access (DMA) engine to process descriptors to control at least one DMA channel, the DMA engine being adapted to:

identify whether a first descriptor of the descriptors is associated with a first descriptor type associated with an immediate write structure;

in response to the identification, store first data of the first descriptor at a location of the I/O memory which is identified by second data of the first descriptor; and

in response to identifying that the first descriptor is associated with the immediate write operation, read first data from a field of the first descriptor associated with an address of the system memory for a descriptor associated with a second descriptor type.

7. The system of claim 6 , wherein the descriptors form at least part of a linked descriptor list.

8. The system of claim 6 , wherein the I/O memory comprises a peripheral-based memory.

9. The system of claim 6 , wherein the DMA engine is further adapted to:

identify whether another descriptor of the descriptors is associated with a data transfer between system memory locations; and

in response to the identification of the another descriptor being associated with the data transfer between the system memory locations, generating a bus operation to perform the data transfer.

10. The system of claim 6 , wherein the DMA engine is further adapted to retrieve at least one of the descriptors from the system memory.

11. The system of claim 6 , wherein the system memory is associated with a first address space, and the I/O memory is associated with a second memory space separate from the first address space.

12. An apparatus comprising:

an integrated circuit comprising a direct memory access (DMA) controller, and a memory,

wherein the DMA controller is adapted to:

process a DMA descriptor to store first data of the DMA descriptor at an address of the memory identified by second data of the descriptor;

determine, based on third data of the DMA descriptor, to identify the DMA descriptor as being associated with a first descriptor type; and

in response to the determination, read the first data from a field of the DMA descriptor, the field being associated with a memory address and being associated with a second descriptor type.

13. The apparatus of claim 12 , wherein the DMA controller is adapted to generate a write operation on a bus, the write operation being associated with the first data and the address of the memory identified by second data of the descriptor.

14. The apparatus of claim 12 , wherein the DMA controller is adapted to perform a single write operation on a bus to store the second data in a I/O memory location identified by the address of the memory identified by second data of the descriptor.

15. The apparatus of claim 12 , wherein the DMA controller is adapted to store the first data in I/O memory.

16. The apparatus of claim 12 , wherein the DMA controller is adapted to process a linked group of DMA descriptors comprising the DMA descriptor processed to store the first data.

17. The apparatus of claim 12 , wherein the memory comprises a memory of a peripheral device.