IP Library Granted Patent US 9,094,020
Granted Patent B2
US 9,094,020 · App. 13/929,415 · Granted Jul 28, 2015

Multi-value logic signaling in multi-functional circuits

Inventors: Marc Loinaz (Los Altos Hills, CA); Stefanos Sidiropoulos (Palo Alto, CA); Whay Sing Lee (Milpitas, CA)
Assignee: Broadcom Corporation
H03L5/00G01R31/2851G06F21/00H03K19/0002
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Quick Facts
Patent No.
US 9,094,020
App. No.
13/929,415
Granted
Jul 28, 2015
Kind
B2
Abstract

An integrated circuit comprises a circuit module, a first function circuit, and a second function circuit. The first function circuit is configured to be operational in response to a first type logic signal at a first pin and the second function circuit is configured to be operational in response to a second type logic signal at the first pin. The type of logic signal at the first pin is determined by the circuit module. Based on the determined type of logic signal, the circuit module is configured to activate the appropriate function circuit and provide function related signaling for operation at a second pin. The circuit module allows the pins of the integrated circuit to be shared between the first and second function circuits, thus minimizing the number of pins required for multi-functional circuits on the integrated circuit.

Claims (77)

1. An integrated circuit, comprising:

a first function circuit configured to be operational in response to a first type of logic signal at a first pin;

a second function circuit configured to be operational in response to a second type of logic signal at the first pin; and

a circuit module configured to:

determine a first difference between a first threshold voltage value and a voltage value at the first pin;

determine a second difference between a second threshold voltage value and the voltage value at the first pin;

determine a type of logic signal at the first pin based on the first difference and the second difference;

detect a digital signal signature at a second pin in response to the determined type being the second type of logic signal; and

activate the second function circuit in response to the detected digital signal signature.

2. The integrated circuit of claim 1 , wherein the first type of logic signal is a binary logic signal, and

wherein the second type of logic signal is a multi-value logic signal.

3. The integrated circuit of claim 1 , wherein the first type of logic signal comprises two logic states, and

wherein the second type of logic signal comprises three or more logic states.

4. The integrated circuit of claim 1 , wherein the circuit module comprises:

a multi-value logic receiver configured to:

determine the type of logic signal at the first pin, and

generate a first activation signal in response to the determined type being the second type of logic signal; and

a signature detection circuit configured to:

detect the digital signal signature at the second pin; and

generate a second activation signal in response to the detected digital signal signature,

wherein the first activation signal from the multi-value logic receiver activates the signature detection circuit, and

wherein the second activation signal from the signature detection circuit activates the second function circuit.

5. The integrated circuit of claim 4 , wherein the signature detection circuit comprises a quiescence detection circuit.

6. The integrated circuit of claim 4 , wherein the signature detection circuit comprises a password detection element.

7. The integrated circuit of claim 4 , wherein the multi-value logic receiver comprises:

a first comparator configured to:

compare the first threshold voltage value and the voltage value at the first pin, and

generate a first comparison signal indicative of the first difference between the first threshold voltage value and the voltage value at the first pin;

a second comparator configured to:

compare the second threshold voltage value and the voltage value at the first pin; and

generate a second comparison signal indicative of the second difference between the second threshold voltage value and the voltage value at the first pin; and

a logic circuit configured to process the first and second comparison signals to determine the type of logic signal at the first pin.

8. The integrated circuit of claim 1 , wherein the circuit module is further configured to generate a deactivation signal to deactivate the second function circuit in response to the determined type being the first type of logic signal.

9. The integrated circuit of claim 1 , wherein the first function circuit comprises a phase-locked loop.

10. A method, comprising:

determining, using a circuit module, a first difference between a first threshold voltage value and a voltage value at a first pin;

determining, using the circuit module, a second difference between a second threshold voltage value and the voltage value at the first pin;

determining, using the circuit module, a type of logic signal at the first pin based on the first difference and the second difference, the type of logic signal being either a first type of logic signal or a second type of logic signal;

detecting, using the circuit module, a digital signal signature at a second pin in response to the second type of logic signal; and

generating, using the circuit module, a signal to switch operation from a first function circuit to a second function circuit in response to the detecting.

11. The method of claim 10 , wherein the first type of logic signal is a binary logic signal, and

wherein the second type of logic signal is a multi-value logic signal.

12. The method of claim 11 , wherein the multi-value logic signal strength falls between a minimum binary signal strength and a maximum binary signal strength.

13. The method of claim 11 , wherein the multi-value logic signal strength falls below a minimum binary signal strength or above a maximum binary signal strength.

14. The method of claim 10 , further comprising generating a signal to activate a signature detection circuit in response to the second type of logic signal.

15. The method of claim 10 , wherein the determining the first difference comprises:

comparing, using a first comparator, the first threshold voltage value and the voltage value at the first pin; and

generating, using the first comparator, a first comparison signal indicative of the first difference between the first threshold voltage value and the voltage value at the first pin,

wherein the determining the second difference comprises:

comparing, using a second comparator, the second threshold voltage value and the voltage value at the first pin;

generating, using the second comparator, a second comparison signal indicative of the second difference between the second threshold voltage value and the voltage value at the first pin, and

wherein the determining the type of logic signal at the first pin comprises:

processing, using a logic circuit, the first and second comparison signals to determine the type of the logic signal at the first pin.

16. The method of claim 10 , further comprising generating a deactivation signal to switch operation to the first function circuit from the second function circuit in response to the first type of logic signal.

17. A circuit, comprising:

a first sub-circuit configured to be operational in response to a first type of logic signal;

a second sub-circuit configured to be operational in response to a second type of logic signal; and

a circuit module configured to:

determine a first difference between a first threshold voltage value and a voltage value at a first pin;

determine a second difference between a second threshold voltage value and the voltage value at the first pin;

determine a type of logic signal at the first pin based on the first difference and the second difference;

detect a digital signal signature at a second pin in response to the determined type being the second type of logic signal;

generate an activation signal to switch operation from the first sub-circuit to the second sub-circuit in response to the detected digital signal signature; and

generate a deactivation signal to switch operation from the second sub-circuit to the first sub-circuit in response to the determined type being the first type of logic signal.

18. The circuit of claim 17 , wherein the first type of logic signal is a binary logic signal, and

wherein the second type of logic signal is a multi-value logic signal.

19. The circuit of claim 17 , wherein the first type of logic signal comprises two logic states, and

wherein the second type of logic signal comprises three or more logic states.

20. The circuit of claim 17 , wherein the circuit module comprises:

a multi-value logic receiver comprising:

a first comparator,

a second comparator,

a logic circuit, and

a filtering circuit; and

a signature detection circuit,

wherein a first activation signal from the multi-value logic receiver activates the signature detection circuit, and

wherein a second activation signal from the signature detection circuit activates the second sub-circuit.

Assignments (9)
CORRECTIVE ASSIGNMENT TO CORRECT THE PATENT NUMBER 9,385,856 TO 9,385,756 PREVIOUSLY RECORDED AT REEL: 47349 FRAME: 001. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Mar 22, 2019
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 051144/0648 →
CORRECTIVE ASSIGNMENT TO CORRECT THE EFFECTIVE DATE PREVIOUSLY RECORDED ON REEL 047229 FRAME 0408. ASSIGNOR(S) HEREBY CONFIRMS THE THE EFFECTIVE DATE IS 09/05/2018. Recorded Oct 29, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047349/0001 →
MERGER Recorded Oct 4, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047229/0408 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: BROADCOM CORPORATION
Reel/Frame 041712/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 1, 2017
From: BROADCOM CORPORATION
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041706/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: BROADCOM CORPORATION
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037806/0001 →
CHANGE OF NAME Recorded Apr 16, 2015
From: NETLOGIC MICROSYSTEMS, INC.
To: NETLOGIC I LLC
Reel/Frame 035443/0824 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 16, 2015
From: NETLOGIC I LLC
To: BROADCOM CORPORATION
Reel/Frame 035443/0763 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 2, 2013
From: LOINAZ, MARC; SIDIROPOULOS, STEFANOS; LEE, WHAY SING
To: NETLOGIC MICROSYSTEMS, INC.
Reel/Frame 030728/0489 →
Continuity (2)
Continuation 12728113 · Mar 19, 2010
Related Publication 20130285736A1 · Oct 31, 2013