Trench liner passivation for dark current improvement
A semiconductor device includes a semiconductor substrate and a trench isolation. The trench isolation is located in the semiconductor substrate, and includes a bottom portion and a top portion. The bottom portion has a lining oxide layer, a negatively-charged liner and a first silicon oxide. The lining oxide layer is peripherally enclosed by the semiconductor substrate, the negatively-charged liner is peripherally enclosed by the lining oxide layer, and the first silicon oxide is peripherally enclosed by the negatively-charged liner. The top portion adjoins the bottom portion, and has a second silicon oxide peripherally enclosed by and contacting the semiconductor substrate.
1. A semiconductor device, comprising:
a semiconductor substrate;
a trench isolation in the semiconductor substrate, the trench isolation comprising:
a lining oxide layer in the trench;
a negative charge liner overlying the lining oxide layer in the trench and being peripherally enclosed by the lining oxide layer;
a bottom portion including a high-K dielectric liner and a first silicon oxide peripherally enclosed by the high-K dielectric liner, wherein the high-K dielectric liner is enclosed by the negative charge liner and contacts the negative charge liner, the negative charge liner is negatively-charged silicon nitride, and the high-K dielectric liner is aluminum oxide or hafnium oxide; and
a top portion adjoining the bottom portion, the top portion including a second silicon oxide with a top surface opposite of a bottom surface, the bottom surface contacting the high-K dielectric liner and the first silicon oxide,
wherein the lining oxide layer extends to the top surface of the top portion and the negative charged liner extends from a top surface of the lining oxide layer in the trench to the top surface of the top portion.
2. The semiconductor device of claim 1 , wherein the negative charge liner has a total negative charge smaller than about −50 E10/cm 2 .
3. The semiconductor device of claim 1 , wherein the semiconductor device is an image sensor or a logic device.
4. The semiconductor device of claim 1 , wherein the first silicon oxide is a cured flowable oxide.
5. The semiconductor device of claim 1 , wherein the first silicon oxide is a cured spin on glass (SOG) layer.
6. The semiconductor device of claim 1 , wherein the second silicon oxide is a high-density plasma (HDP) oxide.
7. The semiconductor device of claim 1 , wherein the second silicon oxide is a planarized oxide.
8. The semiconductor device of claim 1 , wherein the bottom portion is spaced from a top surface of the semiconductor substrate at a distance ranging from 100 Angstroms to 1000 Angstroms.
9. The semiconductor device of claim 1 , wherein the negative charge liner has a total negative charge equal to −100 E10/cm 2 .
10. The semiconductor device of claim 1 , wherein the negative charge liner has a total negative charge equal to −400 E10/cm 2 .