IP Library Granted Patent US 9,054,132
Granted Patent B2
US 9,054,132 · App. 13/930,401 · Granted Jun 9, 2015

Method for manufacturing semiconductor device and semiconductor device

Inventors: Mitsuru Sato (Mie-ken, JP); Masaru Kito (Mie-ken, JP); Megumi Ishiduki (Mie-ken, JP); Ryota Katsumata (Mie-ken, JP)
Assignee: Kabushiki Kaisha Toshiba
H01L29/66666H01L29/7827H01L27/1157H01L27/11582H01L29/66833H01L29/792H01L29/0657
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Quick Facts
Patent No.
US 9,054,132
App. No.
13/930,401
Granted
Jun 9, 2015
Kind
B2
Abstract

According to one embodiment, a method is disclosed for manufacturing a semiconductor device. The second insulating film seals the hole near an interface of the insulating layer and the select gate. The second insulating film is provided on a side wall of the channel body with a space left in the hole above the select gate. The method can include burying a semiconductor film in the space, in addition, forming a conductive film in contact with the channel body.

Claims (47)

1. A method for manufacturing a semiconductor device comprising:

forming a stacked body on a substrate, the stacked body including a select gate and an insulating layer, the insulating layer being provided on the select gate;

forming a hole piercing the stacked body;

forming a first insulating film on a side wall of the hole;

forming a channel body on a side wall of the first insulating film;

forming a second insulating film sealing the hole near an interface of the insulating layer and the select gate, the second insulating film being provided on a side wall of the channel body with a space left in the hole above the select gate and having a film thickness in a side wall portion surrounding the space thinner than a film thickness in a bottom portion sealing the hole;

burying a semiconductor film in the space; and

forming a conductive film in contact with the channel body on an inside of the channel body in the hole on the semiconductor film.

2. The method according to claim 1 , wherein the second insulating film is formed by a film-formation method in which a deposition rate in a vertical direction of the hole is higher than a deposition rate in a lateral direction of the hole.

3. The method according to claim 2 , wherein the second insulating film is formed by a plasma CVD (chemical vapor deposition) method.

4. The method according to claim 1 , wherein the semiconductor film is a non-doped silicon film.

5. The method according to claim 1 , further comprising expanding a hole diameter of a portion surrounded by the insulating layer by wet etching to form a level difference between a side wall of an upper end of the select gate and a side wall of the insulating layer after forming the hole.

6. The method according to claim 1 , further comprising implanting the channel body with an impurity before forming the second insulating film.

7. A method for manufacturing a semiconductor device comprising:

forming a stacked body on a substrate, the stacked body including a select gate and an insulating layer, the insulating layer being provided on the select gate;

forming a hole piercing the stacked body;

forming a first insulating film on a side wall of the hole;

forming a channel body on a side wall of the first insulating film;

forming a second insulating film sealing the hole near an interface of the insulating layer and the select gate, the second insulating film being provided on a side wall of the channel body with a space left in the hole above the select gate;

etching back the second insulating film to remove an upper portion of the second insulating film covering a corner portion between an upper end of the insulating layer and a side wall of the channel body while leaving a bottom portion sealing the hole;

burying a semiconductor film in the space after the etching back the second insulating film; and

forming a conductive film in contact with the channel body on an inside of the channel body in the hole on the semiconductor film.

8. The method according to claim 7 , wherein the second insulating film is formed by an ALD (atomic layer deposition) method.

9. The method according to claim 7 , wherein the semiconductor film is a non-doped silicon film.

10. The method according to claim 7 , further comprising expanding a hole diameter of a portion surrounded by the insulating layer by wet etching to form a level difference between a side wall of an upper end of the select gate and a side wall of the insulating layer after forming the hole.

11. The method according to claim 7 , wherein the second insulating film is etched back by an RIE (reactive ion etching) method.

12. The method according to claim 7 , wherein a side wall portion of the second insulating film is formed in a tapered shape by the etching back.

13. The method according to claim 7 , further comprising implanting the channel body with an impurity before forming the second insulating film.

14. A semiconductor device comprising:

a substrate;

a stacked body including a select gate provided on the substrate and an insulating layer provided on the select gate;

a first insulating film provided on a side wall of a hole piercing the stacked body;

a channel body provided on a side wall of the first insulating film;

a second insulating film sealing the hole near an interface of the insulating layer and the select gate, and provided on a side wall of the channel body above the select gate;

a semiconductor film buried in an inside of the second insulating film in the hole above the select gate; and

a conductive film provided in contact with the channel body on an inside of the channel body in the hole on the semiconductor film,

the second insulating film having a bottom portion sealing the hole, and a side wall portion surrounding a periphery of the semiconductor film, the side wall portion having a film thickness thinner than a film thickness of the bottom portion.

15. The device according to claim 14 , wherein the semiconductor film is a non-doped silicon film.

16. The device according to claim 14 , wherein the conductive film is a silicon film doped with an impurity.

17. The device according to claim 14 , wherein the stacked body further includes:

a plurality of conductive layers provided between the substrate and the select gate; and

a plurality of second insulating layers each provided between adjacent ones of the conductive layers.

18. The device according to claim 17 , further comprising a memory film provided between the conductive layer and the channel body, the memory film including a charge storage film.

19. The device according to claim 14 , wherein a level difference is formed between a side wall of an upper end of the select gate and a side wall of the insulating layer.

20. The device according to claim 19 , wherein

the channel body has a level difference covering portion formed to lie along the level difference and

an impurity concentration of the level difference covering portion is higher than an impurity concentration of a side wall portion above the level difference covering portion in the channel body.

Assignments (5)
CHANGE OF NAME AND ADDRESS Recorded Jan 22, 2021
From: K.K. PANGEA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 055669/0401 →
MERGER Recorded Jan 22, 2021
From: TOSHIBA MEMORY CORPORATION
To: K.K. PANGEA
Reel/Frame 055659/0471 →
CHANGE OF NAME AND ADDRESS Recorded Jan 22, 2021
From: TOSHIBA MEMORY CORPORATION
To: KIOXIA CORPORATION
Reel/Frame 055669/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 24, 2017
From: KABUSHIKI KAISHA TOSHIBA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 043709/0035 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 29, 2013
From: SATO, MITSURU; KITO, MASARU; ISHIDUKI, MEGUMI; KATSUMATA, RYOTA
To: KABUSHIKI KAISHA TOSHIBA
Reel/Frame 030894/0383 →
Priority Claims (1)
JP 2012-148617 · Jul 2, 2012 · national
Continuity (1)
Related Publication 20140001544A1 · Jan 2, 2014