PHASE SWITCHABLE BISTABLE MEMORY DEVICE, A FREQUENCY DIVIDER AND A RADIO FREQUENCY TRANSCEIVER
A phase switchable bistable memory device comprising a bistable memory component and a phase switching component is described. The bistable memory component comprises a bistable memory stage arranged to receive an input signal and a state transition stage arranged to receive a state transition signal and to cause the bistable memory stage to capture a logical state of the received input signal upon a transition from a first logical state of the state transition signal to a second logical state of the state transition signal. The phase switching component is arranged to receive a clock input signal and a phase control signal, and to output the state transition signal comprising transitions between logical states corresponding to transitions between logical states of the clock input signal and comprising a phase relative to the clock input signal based at least partly on the received phase control signal.
1 . A phase switchable bistable memory device comprising:
a bistable memory component and a phase switching component, the bistable memory component comprises:
a bistable memory stage arranged to receive an input signal; and
a state transition stage arranged to receive a state transition signal and to cause the bistable memory stage to capture a logical state of the received input signal upon a transition from a first logical state of the state transition signal to a second logical state of the state transition signal;
wherein the phase switching component is arranged to receive a clock input signal and a phase control signal, and to output the state transition signal comprising transitions between logical states corresponding to transitions between logical states of the clock input signal and comprising a phase relative to the clock input signal based at least partly on the received phase control signal.
2 . The phase switchable bistable memory device of claim 1 , wherein the phase switching component is arranged to output a state transition signal comprising one of:
a phase that matches a phase of the clock input signal; and
a phase inverted relative to a phase of the clock input signal,
dependent upon a logical state of the phase control signal.
3 . The phase switchable bistable memory device of claim 1 wherein the bistable memory component and the phase switching component are operably coupled in parallel between voltages supply rails.
4 . The phase switchable bistable memory device of claim 1 , wherein the phase switching component comprises a clock input stage arranged to receive the clock input signal and to drive the state transition signal in accordance with the received clock signal.
5 . The phase switchable bistable memory device of claim 4 further comprising a phase switching stage operably coupled between the clock input stage and the bistable memory component, and arranged to receive the phase control signal and to configure a phase of the state transition signal in accordance with the phase control signal.
6 . The phase switchable bistable memory device of claim 5 , wherein the phase switching stage comprises a set of emitter coupled transistor pairs arranged to enable differential components of the state transition signal driven by the clock input stage to be swapped in accordance with the phase control signal.
7 . The phase switchable bistable memory device of claim 1 , wherein the phase switchable bistable memory device comprises a differential topology.
8 . The phase switchable bistable memory device of claim 1 , wherein the bistable memory stage of the bistable memory component comprises two cross-coupled switching element pairs; a first of the cross-coupled switching element pairs being arranged to capture a logical state of a differential input signal upon a transition from a first logical state of the state transition signal to a second logical state of the state transition signal, and the second of the cross-coupled switching element pairs being arranged to latch a logical state captured by the first of the cross-coupled switching element pairs when the state transition signal comprises the first logical state.
9 . The phase switchable bistable memory device of claim 8 , wherein the state transition stage of the bistable memory component comprises two switching elements operably coupled between the bistable memory stage and a low voltage supply rail, such that each switching element is arranged to selectively couple a respective cross-coupled switching element pair of the bistable memory stage to the low voltage supply rail in accordance with a respective component of the differential state transition signal.
10 . The phase switchable bistable memory device of claim 1 , wherein the phase switchable bistable memory device comprises emitter coupled logic.
11 . The phase switchable bistable memory device of claim 1 , wherein the phase switchable bistable memory device further comprises an emitter follower operably coupled between each output of the phase switching component and each respective input of the state transition stage of the bistable memory component.
12 . The phase switchable bistable memory device of claim 1 , wherein the bistable memory component comprises a flip-flop.
13 . The phase switchable bistable memory device of claim 1 , wherein the phase switching stage comprises an eXclusive OR gate.
14 . The phase switchable bistable memory device of claim 1 , wherein the phase switchable bistable memory device further comprises a current mirror component comprising at least one current mirror circuit operably coupled between the bistable memory component and a voltage supply rail.
15 . The phase switchable bistable memory device of claim 14 , wherein the current mirror component further comprises at least one current mirror circuit operably coupled between the phase switching component and the voltage supply rail.
16 . The phase switchable bistable memory device of claim 1 , when implemented within an integrated circuit device comprising at least one die within a single integrated circuit package.
17 . A frequency divider comprising at least one phase switchable bistable memory device according to claim 1 .
18 . The frequency divider of claim 17 , wherein the frequency divider comprises a divide-by-three frequency divider.
19 . A radio frequency (RF) transceiver comprising at least one frequency divider according to claim 17 .
20 . A radio frequency (RF) transceiver of claim 19 , wherein the phase switching component comprises a clock input stage arranged to receive the clock input signal and to drive the state transition signal in accordance with the received clock signal.