Patent Assignment
Reel/Frame 031627/0201
Supplement to Ip Security Agreement
Recorded: 2013-11-13
Pages: 20
Assignor
FREESCALE SEMICONDUCTOR, INC.
Executed: 2013-11-01
Assignee
CITIBANK, N.A., AS NOTES COLLATERAL AGENT
390 GREENWICH STREET, NEW YORK, NEW YORK, 10013
Covered Properties
(148)
Debug Method and Device for Providing Indexed Trace Messages
Debug Method and Device for Handling Exceptions and Interrupts
Phase Switchable Bistable Memory Device, a Frequency Divider and a Radio Frequency Transceiver
Application:
13/933,527 →
Publication:
US 2015/0009747
Communication Device for Wideband Code Division Multiple Access Communication (W-Cdma) System, a Method for Use Therein and an Associated Semiconductor Device
Using an Integrated Circuit Die Configuration for Package Height Reduction
System and Method for Atomically Updating Shared Memory in Multiprocessor System
Application:
13/935,550 →
Publication:
US 2015/0012711
Digital Self-Gated Binary Counter
System for Compensating for Dynamic Skew in Memory Devices
Application:
13/935,554 →
Publication:
US 2015/0012718
Quad Flat Semiconductor Device with Additional Contacts
Hybrid Lead Frame and Ball Grid Array Package
Wireless Communication Apparatus and Method
System for Functional Reset Across Multiple Clock Domains
Patent:
8,890,594 →
Application:
13/938,244 →
Wireless Communication Apparatus and Method
Receiver Configurable in a Plurality of Modes
Application:
13/938,677 →
Publication:
US 2013/0303099
Semiconductor Device with Corner Tie Bars
Systems and Methods for Reducing Power Consumption in Semiconductor Devices
Pressure Sensor Having Down-Set Flag
Application:
13/941,556 →
Publication:
US 2015/0014793
Microelectronic Packages Having Frontside Thermal Contacts and Methods for the Fabrication Thereof
Microelectronic Packages and Methods for the Fabrication Thereof
Adaptive Erase Recovery for Non-Volatile Memory (Nvm) Systems
Least Recently Used (Lru) Cache Replacement Implementation Using a Fifo Storing Indications of Whether a Way of the Cache Was Most Recently Accessed
Wire Bonding Capillary with Working Tip Protrusion
Redistributed Chip Packages Containing Multiple Components and Methods for the Fabrication Thereof
Patent:
8,822,268 →
Application:
13/944,774 →
Backscattering for Localized Annealing
Modular Gray Code Counter
Patent:
8,867,694 →
Application:
13/945,937 →
Protection Device and Related Fabrication Methods
Reducing Microelectromechanical Systems Stiction by Formation of a Silicon Carbide Layer
Mems Parameter Identification Using Modulated Waveforms
Semiconductor Wafer Plating Bus and Method for Forming
System and Method for Lead Frame Package Degating
Circuitry for a Computing System, Lsu Arrangement and Memory Arrangement as Well as Computing System
Method and System for Facilitating Viewing of Information in a Machine
Switch-Mode Amplifier
Split Gate Non-Volatile Memory Cell
Data Processor Device Having a Debug Control Module Which Selectively Modifies Trace Messages
Systems and Methods for Locking Branch Target Buffer Entries
Non-Volatile Memory (Nvm) and High-K and Metal Gate Integration Using Gate-First Methodology
Patent:
8,871,598 →
Application:
13/955,665 →
Stress Migration Mitigation
Capping Layer Interface Interruption for Stress Migration Mitigation
Data Processing System with Protocol Determination Circuitry
Integrated Circuit with Degradation Monitoring
Coupler with Distributed Feeding and Compensation
Electronic Device for Detecting Erronous Key Selection Entry
Self-Adapting Voltage Amplifier and Battery Charger Detection
Adjustable Power Splitter and Corresponding Methods & Apparatus
Master-Slave Flip-Flop with Low Power Consumption
Mems Device with Differential Vertical Sense Electrodes
Split Gate Memory Device with Gap Spacer
Nonvolatile Memory Bitcell with Inlaid High K Metal Select Gate
Cache Organization and Method
Transducer-Including Devices, and Methods and Apparatus for Their Calibration
Embedded Software Debug System with Partial Hardware Acceleration
Electronic Device with Power Mode Control Buffers
Bask Demodulator and Method for Demodulating Bask Modulated Signal
Techniques for Electromigration Stress Determination in Interconnects of an Integrated Circuit
Complementary Gallium Nitride Integrated Circuits
Application:
13/964,778 →
Publication:
US 2015/0041820
Method for Verifying Digital to Analog Converter Design
State Retention Power Gated Cell
Extended Protection For Embedded Erase Of Non-Volatile Memory Cells
Built-In Self Test (Bist) with Clock Control
Test Structure and Methodology for Estimating Sensitivity of Pressure Sensors
Data Bus Network Interface Module and Method Therefor
Non-Volatile Memory (Nvm) Cell, High Voltage Transistor, and High-K and Metal Gate Transistor Integration
Patent:
8,877,585 →
Application:
13/969,180 →
Steering Traffic Among Multiple Network Services Using a Centralized Dispatcher
Split-Gate Non-Volatile Memory Cells Having Gap Protection Zones
Redundant Signed Digit (Rsd) Analog to Digital Converter
Patent:
8,860,596 →
Application:
13/971,007 →
Secure Provisioning in an Untrusted Environment
Integrated Split Gate Non-Volatile Memory Cell and Logic Structure
Level Shifter with Static Precharge Circuit
Integrated Split Gate Non-Volatile Memory Cell and Logic Device
Solder Wettable Flanges and Devices and Systems Incorporating Solder Wettable Flanges
Lead Frame Based Semiconductor Die Package
Decryption Key Management System
Semiconductor Device with Self-Biased Isolation
Method to Form a Polysilicon Nanocrystal Thin Film Storage Bitcell Within a High K Metal Gate Platform Technology Using a Gate Last Process to Form Transistor Gates
Split-Gate Non-Volatile Memory (Nvm) Cell and Device Structure Integration
Patent:
8,932,925 →
Application:
13/973,549 →
Power Switch with Current Limitation and Zero Direct Current (Dc) Power Consumption
Pressure Sensor Device and Assembly Method
Application:
13/975,359 →
Publication:
US 2015/0054099
Integrated Circuit Device and Method for Determining an Index of an Extreme Value Within an Array of Values
Transmitter and Method of Operating a Transmitter
Device and Method for Computing a Function Value of a Function
Integrated Circuit Device, Voltage Regulation Circuitry and Method for Regulating a Voltage Supply Signal
Integrated Circuit Devices and Methods for Instruction Scheduling and Executing a Restricted Load Operation Speculatively Scheduled Ahead of a Scheduling Restriction
Application:
13/982,854 →
Publication:
US 2013/0326200
Integrated Circuit Device, Power Management Module and Method for Providing Power Management
Overcurrent Protection Device and Method of Operating a Power Switch
Application:
13/983,150 →
Publication:
US 2013/0314832
Semiconductor Device and Related Fabrication Methods
Overcurrent Protection Device and Method of Operating a Power Switch
Integrated Circuit Device, Electronic Device and Method for Frequency Detection
Method for Ranking Paths for Power Optimization of an Integrated Circuit Design and Corresponding Computer Program Product
Integrated Circuit Device and Methods of Performing Bit Manipulation Therefor
Integrated Circuit Device and Method for Enabling Cross-Context Access
Application:
14/006,022 →
Publication:
US 2014/0019990
Processor System with Predicate Register, Computer System, Method for Managing Predicates and Computer Program Product
Integrated Circuit and Method for Reducing an Impact of Electrical Stress in an Integrated Circuit
Integrated Circuit Device and Methods for Performing Cut-Through Forwarding
Apparatus for Forward Well Bias in a Semiconductor Integrated Circuit
Application:
14/008,581 →
Publication:
US 2014/0021557
Method and Apparatus for Controlling Fetch-Ahead in a Vles Processor Architecture
Receiver Device, Multi-Frequency Radar System and Vehicle
Application:
14/009,009 →
Publication:
US 2014/0197983
Amplfiers and Related Integrated Circuits
Pressure Sensor Device Having Bump Chip Carrier (Bcc)
Patent:
8,941,194 →
Application:
14/010,557 →
Method for Forming a Packaged Semiconductor Device
Sequential Wafer Bonding
Negative Voltage Measurement
Electro-Mechanical Oscillator and Common-Mode Detection Circuit
Microelectronic Packages Containing Opposing Devices and Methods for the Fabrication Thereof
Split Gate Nanocrystal Memory Integration
Systems and Methods for Secure Boot Rom Patch
Clock Glitch Detection Circuit
Secure Firmware Flash Controller
Application:
14/015,889 →
Publication:
US 2015/0067314
Method and Circuit for Controlling Turnoff of a Semiconductor Switching Element
Single Port Memory That Emulates Dual Port Memory
Electronic Device Including Interconnects with a Cavity Therebetween and a Process of Forming the Same
Wafer-Level Gate Stress Testing
Edge Coupling of Semiconductor Dies
Cavity Based Packaging for Mems Devices
Multiple Sense Axis Mems Gyroscope Having a Single Drive Mode
Methods of Forming Electronic Elements with Esd Protection
Package-On-Package Semiconductor Sensor Device
Application:
14/020,840 →
Publication:
US 2015/0069537
Copper Pillar Bump and Flip Chip Package Using Same
Method of Forming Different Voltage Devices with High-K Metal Gate
Methods For Forming Contact Landing Regions In Split-Gate Non-Volatile Memory (NVM) Cell Arrays
Master-Slave Flip-Flop with Reduced Setup Time
Patent:
8,908,449 →
Application:
14/022,872 →
Non-Volatile Memory (Nvm) Cell and High-K and Metal Gate Transistor Integration
Universal Spi (Serial Peripheral Interface)
Recessed Semiconductor Die Stack
Application:
14/024,742 →
Publication:
US 2015/0069624
System and Method for Data Synchronization Across Digital Device Interfaces
Semiconductor Device and Lead Frame with Interposer
Application:
14/029,766 →
Publication:
US 2015/0075849
Heat Spreader for Integrated Circuit Device
Side Vented Pressure Sensor Device
Squib Driver Diagnostic Circuit and Method
System-In-Packages Containing Embedded Surface Mount Devices and Methods for the Fabrication Thereof
Application:
14/030,952 →
Publication:
US 2015/0076700
Non-Volatile Memory (Nvm) with Dynamically Adjusted Reference Current
Stacked Protection Devices and Related Fabrication Methods
Temperature Dependent Biasing for Leakage Power Reduction
Package Encapsulant Relief Feature
Memory Having One Time Programmable (Otp) Elements and a Method of Programming the Memory
System and Method for Enabling Maximum Performance Operation Within an Extended Ambient Temperature Range
3D Device Packaging Using Through-Substrate Pillars
Method and Device for Generating Floating-Point Values
Method of Making a Floating Gate Non-Volatile Memory (Nvm) with Breakdown Prevention
Application:
14/041,449 →
Publication:
US 2015/0093863
Non-Volatile Memory (Nvm) and High-K and Metal Gate Integration Using Gate-Last Methodology
Non-Volatile Memory (Nvm) and High-K and Metal Gate Integration Using Gate-First Methodology
Non-Volatile Memory (Nvm) and High-K and Metal Gate Integration Using Gate-Last Methodology
Patent:
8,901,632 →
Application:
14/041,662 →
Dynamic Programming for Flash Memory
Data Processing System with Cache Linefill Buffer and Method of Operation
Mold Locks for Laminate Substrates
Application:
14/041,968 →
Publication:
US 2015/0091196
Devices and Stacked Microelectronic Packages with Parallel Conductors and Intra-Conductor Isolator Structures and Methods of Their Fabrication
Devices and Stacked Microelectronic Packages with in-Trench Package Surface Conductors and Methods of Their Fabrication
Electronic Component Package and Method for Forming Same
Related Assignments
(25)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignor's Interest
Jul 1, 2013
From: EHRLICH, ROBERT N.; MCGOWAN, ROBERT A.; SCHINZLER, MICHAEL B.
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 030718/0986 →
Assignment of Assignor's Interest
Jul 1, 2013
From: MCGOWAN, ROBERT A.; EHRLICH, ROBERT N.
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 030718/0898 →
Assignment of Assignor's Interest
Jul 2, 2013
From: NEEMAN, YUVAL; BAR-OR, AMIT; BEZALEL, KFIR; SHAHAR, YOEL
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 030729/0182 →
Assignment of Assignor's Interest
Jul 2, 2013
From: GHAZINOUR, AKBAR; TROTTA, SAVERIO
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 030728/0329 →
Assignment of Assignor's Interest
Jul 3, 2013
From: PHAM, TIM V.; GUAJARDO, JAMES R.; MCSHANE, MICHAEL B.
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 030737/0902 →
Assignment of Assignor's Interest
Jul 4, 2013
From: GARG, VAKUL; SETHI, VARUN; BHUSHAN, BHARAT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 030741/0028 →
Assignment of Assignor's Interest
Jul 5, 2013
From: GUPTA, ATUL; GAITE, AJAY
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 030741/0034 →
Assignment of Assignor's Interest
Jul 5, 2013
From: GUPTA, NAMAN; AGARWAL, AMOL; GOYAL, GAURAV
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 030741/0039 →
Assignment of Assignor's Interest
Jul 10, 2013
From: KACZMAN, DANIEL L; SHAH, MANISH N.
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 030769/0583 →
Assignment of Assignor's Interest
Jul 10, 2013
From: GARG, ARVIND; DAHIYA, SOMVIR; JAIN, SACHIN; KAUSHIK, ARVIND
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 030763/0217 →
Assignment of Assignor's Interest
Jul 10, 2013
From: TENG, SENG KIONG; KHOO, LY HOON; KALANDAR, NAVAS KHAN ORATTI
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 030763/0131 →
Assignment of Assignor's Interest
Jul 10, 2013
From: TIU, KONG BEE; IBRAHIM, RUZAINI B.; LO, WAI YEW
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 030763/0141 →
Assignment of Assignor's Interest
Jul 10, 2013
From: TADI, SURENDRA KUMAR; JAISWAL, NITIN KUMAR
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 030763/0201 →
Assignment of Assignor's Interest
Jul 10, 2013
From: JAIN, SACHIN; DAHIYA, SOMVIR; GARG, ARVIND; KAUSHIK, ARVIND
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 030763/0163 →
Assignment of Assignor's Interest
Jul 11, 2013
From: CHAN, WENG HOONG; KHOO, LY HOON; LOW, BOON YEW
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 030772/0666 →
Assignment of Assignor's Interest
Jul 12, 2013
From: JARRAR, ANIS M.; HALL, MARK D.; TIPPLE, DAVID R.; VEERARAGHAVAN, SURYA
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 030787/0528 →
Assignment of Assignor's Interest
Jul 15, 2013
From: YAP, WENG F.; MITCHELL, DOUGLAS G.
To: FREESCALE SEMICONDUCTOR INC.
Reel/Frame 030800/0569 →
Assignment of Assignor's Interest
Jul 15, 2013
From: YAP, WENG F.; MITCHELL, DOUGLAS G.
To: FREESCALE SEMICONDUCTOR INC.
Reel/Frame 030800/0644 →
Assignment of Assignor's Interest
Jul 15, 2013
From: YOW, KAI YUN; EU, POH LENG
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 030792/0466 →
Security Agreement
Nov 6, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 031591/0266 →
Supplement to Ip Security Agreement
Nov 13, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS COLLATERAL AGENT
Reel/Frame 031627/0158 →
Patent Release
Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0874 →
Assignment and Assumption of Security Interest in Patents
Jan 5, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037444/0787 →
Assignment and Assumption of Security Interest in Patents
Jan 13, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037518/0292 →
Security Agreement Supplement
Mar 7, 2016
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 038017/0058 →