Granted Patent B2

US 9,171,117 · App. 14/003,361 · Granted Oct 27, 2015

Abstract

Claims (102)

1. A method for ranking paths for power optimization of an integrated circuit design, comprising:

identifying, by a computer system, a plurality of paths of the integrated circuit design, each path comprising one or more instances of electronic devices;

providing an instance power estimate for each instance in the identified paths;

providing, for each identified path, at least one weighted power estimate based on the instance power estimates for instances in the path;

providing a ranking of the paths based on the least one weighted power estimate, wherein the at least one weighted power estimate comprises at least one of:

(a) a distance weighted power estimate for each path calculated as

D

=

1

I

·

∑

i

⁢

⁢

p

i

⁢

wherein pi corresponds to the instance power estimate of instance i in the path and I corresponds to the total number of instances in the path;

(b) a logic distance weighted power estimate for each path calculated as

L

=

∑

i

⁢

⁢

p

i

c

i

wherein pi corresponds to the instance power estimate of instance i in the path and ci corresponds to a predetermined complexity value assigned to instance I; and

(c) a timing weighted power estimate for each path calculated as

T

=

∑

i

⁢

⁢

p

i

s

i

wherein pi corresponds to the instance power estimate of instance i in the path and si corresponds to the time a signal needs to propagate through instance i; and

producing an integrated circuit based on the ranking of the paths in the integrated circuit design.

2. The method of claim 1 , further comprising optimizing at least one the ranked paths for power utilization.

3. The method of claim 1 , further comprising adding one or more sampling stages to a path determined for power optimization.

4. The method of claim 1 , wherein critical paths are given a low rank by the at least one weighted power estimate.

5. The method of claim 1 , wherein the paths are ranked according to more than one weighted power estimate.

6. The method of claim 1 , wherein the at least one weighted power estimate is the distance weighted power estimate.

7. The method of claim 1 , wherein the at least one weighted power estimate is the logic distance weighted power estimate.

8. The method of claim 1 , wherein ci corresponds to a number of inputs of instance i in the path, defining a complexity value assigned to instance i.

9. The method of claim 1 , wherein the at least one weighted power estimate is the timing weighted power estimate.

10. The method of claim 1 , further comprising a timing optimizing of the integrated circuit design.

11. The method of claim 1 , the method being performed based on a Register Transfer Level representation of the integrated circuit design.

12. The method of claim 1 , wherein identifying a plurality of paths comprises identifying a plurality of non-critical paths.

13. A non-transitory computer-readable medium, comprising instructions, that when executed by a computer system perform a method for ranking paths for power optimization of an integrated circuit design, the method comprising:

identifying a plurality of paths of the integrated circuit design, each path comprising one or more instances of electronic devices;

providing an instance power estimate for each instance in the identified paths;

providing, for each identified path, at least one weighted power estimate based on the instance power estimates for instances in the path, and providing a ranking of the paths based on the least one weighted power estimate;

wherein the at least one weighted power estimate comprises at least one of:

(a) a distance weighted power estimate for each path calculated as

D

=

1

l

·

∑

i

⁢

p

i

wherein pi corresponds to the instance power estimate of instance i in the path and I corresponds to the total number of instances in the path;

(b) a logic distance weighted power estimate for each path calculated as

L

=

∑

i

⁢

p

i

c

i

wherein pi corresponds to the instance power estimate of instance i in the path and ci corresponds to a predetermined complexity value assigned to instance I; and

(c) a timing weighted power estimate for each path calculated as

T

=

∑

i

⁢

p

i

s

i

wherein pi corresponds to the instance power estimate of instance i in the path and si corresponds to the time a signal needs to propagate through instance i; and

producing an integrated circuit based on the ranking of the paths in the integrated circuit design.

14. The computer readable medium of claim 13 , wherein the method further comprises optimizing at least one the ranked paths for power utilization.

15. The computer readable medium of claim 13 , wherein the method further comprises adding one or more sampling stages to a path determined for power optimization.

16. The computer readable medium of claim 13 , wherein critical paths are given a low rank by the at least one weighted power estimate.

17. The computer readable medium of claim 13 , wherein the paths are ranked according to more than one weighted power estimate.

18. The method of claim 13 , wherein the at least one weighted power estimate is the distance weighted power estimate.

19. The method of claim 13 , wherein the at least one weighted power estimate is the logic distance weighted power estimate.

20. The method of claim 13 , wherein the at least one weighted power estimate is the timing weighted power estimate.

Assignments (27)