Master-slave flip-flop with low power consumption
In a master-slave flip-flop, the master latch has first and second three-state stages, and a first feedback stage. The slave latch has third and fourth three-state stages, and a second feedback stage. First and second clock switches having opposite phases are provided. The first clock switch is configured in one of the first and fourth three-state stages, and the other stage shares the first clock switch. The second clock switch is configured in one of the second and third three-state stages, and the other stage shares the second clock switch. The second three-state stage has an additional pair of complementary devices having signal paths connected in series with each other with both being gated by a data output of the slave latch. The flip-flop reduces the number of clock switches and clock switch power consumption.
1. A flip-flop, comprising:
a master latch having first and second three-state stages respectively having a first pair of complementary semiconductor devices gated by a data input of the first three-state stage and a second pair of complementary semiconductor devices gated by a data input of the second three-state stage, and a first feedback stage for positive feedback from data outputs of the first and second three-state stages to the data input of the second three-state stage; and
a slave latch connected to the master latch, and having third and fourth three-state stages, the third and fourth three-state stages respectively having a third pair of complementary semiconductor devices gated by a data input of the third three-state stage and a fourth pair of complementary semiconductor devices gated by a data input of the fourth three-state stage, and a second feedback stage for positive feedback from data outputs of the third and fourth three-state stages to the data input of the fourth three-state stage,
wherein a first clock switch that receives clock signals from a clock signal source is configured in one of the first and fourth three-state stages, and the other one of the first and fourth three-state stages shares the first clock switch, and a second clock switch that receives clock signals from the clock signal source is configured in one of the second and third three-state stages, and the other one of the second and third three-state stages shares the second clock switch, and the first and second clock switches have opposite phases, and
wherein the second three-state stage further includes an additional pair of complementary semiconductor devices having signal paths connected in series with each other and both being gated by a data output of the slave latch.
2. The flip-flop of claim 1 , wherein the first, second, third and fourth pairs of complementary semiconductor devices have respective signal paths connected in series with each other and in series with one of the first and second clock switches, and the additional pair of complementary semiconductor devices have signal paths connected in series with the second pair of complementary semiconductor devices.
3. The flip-flop of claim 2 , wherein positions of a PMOS of the second pair of complementary semiconductor devices and that of the additional pair of complementary semiconductor devices are exchangeable, and positions of a NMOS of the second pair of complementary semiconductor devices and that of the additional pair of complementary semiconductor devices are exchangeable.
4. The flip-flop of claim 1 , wherein the first clock switch is configured in the first three-state stage, and the second clock switch is configured in the second three-state stage.
5. The flip-flop of claim 1 , wherein the first clock switch is configured in the first three-state stage, and the second clock switch is configured in the third three-state stage.
6. The flip-flop of claim 1 , wherein the first clock switch is configured in the fourth three-state stage, and the second clock switch is configured in the second three-state stage.
7. The flip-flop of claim 1 , wherein the first clock switch is configured in the fourth three-state stage, and the second clock switch is configured in the third three-state stage.
8. The flip-flop of claim 1 , wherein the first and second clock switches are respectively connected to a power supply.
9. A method of operating a flip-flop, said flip-flop comprising a master latch having first and second three-state stages respectively having a first pair of complementary semiconductor devices gated by a data input of said first three-state stage and a second pair of complementary semiconductor devices gated by a data input of said second three-state stage, and a first feedback stage for positive feedback from data outputs of said first and second three-state stages to said data input of said second three-state stage, and a slave latch connected to said master latch, said slave latch having third and fourth three-state stages having respectively a third pair of complementary semiconductor devices gated by a data input of said third three-state stage and a fourth pair of complementary semiconductor devices gated by a data input of said fourth three-state stage, and a second feedback stage for positive feedback from data outputs of said third and fourth three-state stages to said data input of said fourth three-state stage, the method comprising:
applying a data input signal to said data input of said first three-state stage;
applying a clock input signal to first and second clock switches, wherein the first clock switch that receives clock signals from a clock signal source is configured in one of said first and fourth three-state stages, and the other one of said first and fourth three-state stages shares the first clock switch, and a second clock switch that receives clock signals from said clock signal source is configured in one of said second and third three-state stages, and the other of said second and third three-state stage shares the second clock switch, wherein the first and second clock switches have opposite phases, and wherein the second three-state stage further includes an additional pair of complementary semiconductor devices having signal paths connected in series with each other and both being gated by a data output of said slave latch.
10. The method of claim 9 , wherein said first, second, third and fourth pair of complementary semiconductor devices have respective signal paths connected in series with each other and in series with one of said first and second clock switches, and said additional pair of complementary semiconductor devices have signal paths connected in series with the second pair of complementary semiconductor devices.
11. The method of claim 10 , wherein positions of a PMOS of the second pair of complementary semiconductor devices and that of the additional pair of complementary semiconductor devices are exchangeable, and positions of a NMOS of the second pair of complementary semiconductor devices and that of the additional pair of complementary semiconductor devices are exchangeable.
12. The method of claim 9 , wherein said first clock switch is configured in said first three-state stage, and the second clock switch is configured in said second three-state stage.
13. The method of claim 9 , wherein said first clock switch is configured in said first three-state stage, and the second clock switch is configured in said third three-state stage.
14. The method of claim 9 , wherein said first clock switch is configured in said fourth three-state stage, and the second clock switch is configured in said second three-state stage.
15. The method of claim 9 , wherein said first clock switch is configured in said fourth three-state stage, and the second clock switch is configured in said third three-state stage.
16. The method of claim 9 , wherein said first and second clock switch are respectively connected to a power supply.