Methods for forming contact landing regions in split-gate non-volatile memory (NVM) cell arrays
View Patent ↗Methods and related structures are disclosed for forming contact landing regions in split-gate NVM (non-volatile memory) systems. A dummy select gate structure is formed while also forming select gates for split-gate NVM cells. A control gate layer is formed over the select gates and the dummy select gate structure, as well as an intervening charge storage layer. The control gate material will fill in gaps between the select gate material and the dummy select gate material. A non-patterned spacer etch is then used to etch the control gate layer to form a contact landing region associated with the dummy select gate structure while also forming spacer control gates for the split-gate NVM cells. The disclosed embodiments provide improved (e.g., more planar) contact landing regions without requiring additional processing steps and without increasing the pitch of the resulting NVM cell array.
1. A method for forming a contact landing region for a split-gate non-volatile memory (NVM) system, comprising:
forming select gate structures for split-gate non-volatile memory (NVM) cells within an array of split-gate NVM cells;
forming a dummy select gate structure while forming the select gate structures;
forming a charge storage layer for the split-gate NVM cells;
forming a control gate layer over the select gate structures and the dummy select gate structure; and
etching the control gate layer with a non-patterned spacer etch to form control gate structures associated with the split-gate NVM cells and to form a contact landing region between the select gate structures and the dummy select gate structure.
2. The method of claim 1 , wherein a distance from an edge for the dummy select gate structure to an edge for a select gate structure is equal to or less than about 1.5 to 2.0 times the thickness of the control gate layer.
3. The method of claim 1 , further comprising forming an electrical contact coupled to the contact landing region.
4. The method of claim 1 , wherein a plurality of dummy select gate structures are formed and wherein the etching step forms a plurality of control gate structures and contact landing regions.
5. The method of claim 1 , wherein the forming the dummy select gate structure step comprises forming a dummy select gate structure between two select gate lines within the array of NVM cells.
6. The method of claim 5 , wherein the etching step leaves a control-gate strap between the two select gate lines that includes the dummy select gate structure.
7. The method of claim 5 , further comprising forming at least one select-gate tab while forming the select gate structures, the select-gate tab extending from a select gate structure towards the dummy select gate structure.
8. The method of claim 1 , wherein the forming the dummy select gate structure step comprises forming a dummy select gate structure at the longitudinal ends of two select gate lines within the array of NVM cells.
9. The method of claim 8 , wherein the etching step leaves a control-gate wrap connection adjacent the two select gate lines that includes the dummy select gate structure.
10. The method of claim 8 , further comprising forming an additional dummy select gate structure between the two select gate lines while forming the select gate structures.
11. The method of claim 10 , wherein the etching step leaves an additional contact landing region between the dummy select gate structure and the additional dummy select gate structure.
12. The method of claim 11 , wherein the etching step further leaves an additional contact landing region between the additional dummy select gate structure and the select gate structure.
13. The method of claim 1 , wherein the contact landing region comprises a sloped edge extending from the select gate structure and a sloped edge extending from the dummy select gate structure.