IP Library Granted Patent US 9,543,420
Granted Patent B2
US 9,543,420 · App. 13/946,613 · Granted Jan 10, 2017

Protection device and related fabrication methods

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Quick Facts
Patent No.
US 9,543,420
App. No.
13/946,613
Granted
Jan 10, 2017
Kind
B2
Abstract

Protection device structures and related fabrication methods are provided. An exemplary semiconductor protection device includes a base region of semiconductor material having a first conductivity type, an emitter region within the base region having the opposite conductivity type, and a collector region of semiconductor material having the second conductivity type, wherein at least a portion of the base region resides between the emitter region and the collector region. A depth of the collector region is greater than a depth of the emitter region and less than or equal to a depth of the base region such that a distance between a lateral boundary of the emitter region and a proximal lateral boundary of the collector region is greater than zero and the collector region does not overlap or otherwise underlie the emitter region.

Claims (81)

1. A semiconductor device comprising:

a first region of semiconductor material having a first conductivity type and a first dopant concentration;

a base well region within the first region, the base well region having the first conductivity type and a second dopant concentration greater than the first dopant concentration of the first region;

a base contact region within the base well region, the base contact region having the first conductivity type and a third dopant concentration greater than the first dopant concentration;

an emitter region of semiconductor material within the base well region, the emitter region having a second conductivity type opposite the first conductivity type; and

a collector region of semiconductor material having the second conductivity type, wherein:

at least a portion of the first region resides between the emitter region and the collector region;

a depth of the collector region is greater than a depth of the emitter region;

a depth of a second portion of the first region underlying the emitter region is greater than or equal to the depth of the collector region;

at least a portion of the base well region resides between the emitter region and the collector region; and

the depth of the collector region is greater than a depth of the base well region.

2. A semiconductor device comprising:

a first region of semiconductor material having a first conductivity type and a first dopant concentration;

a base well region within the first region, the base well region having the first conductivity type and a second dopant concentration greater than the first dopant concentration of the first region;

a base contact region within the base well region, the base contact region having the first conductivity type and a third dopant concentration greater than the first dopant concentration;

an emitter region of semiconductor material within the base well region, the emitter region having a second conductivity type opposite the first conductivity type; and

a collector region of semiconductor material having the second conductivity type, wherein:

at least a portion of the first region resides between the emitter region and the collector region;

a depth of the collector region is greater than a depth of the emitter region;

a depth of a second portion of the first region underlying the emitter region is greater than or equal to the depth of the collector region; and

the collector region comprises:

a well region of semiconductor material having the second conductivity type and a first dopant concentration; and

a buried region of semiconductor material underlying the well region, the buried region having the second conductivity type and a second dopant concentration greater than or equal to the first dopant concentration.

3. A semiconductor device comprising:

a first region of semiconductor material having a first conductivity type;

an emitter region of semiconductor material having a second conductivity type opposite the first conductivity type;

a collector region of semiconductor material having the second conductivity type; and

a base well region within the first region, the base well region having the emitter region formed therein, the base well region having the first conductivity type and a first dopant concentration greater than a second dopant concentration of the first region by a factor of at least 10, wherein:

at least a portion of the first region resides between the emitter region and the collector region;

a depth of the collector region is greater than a depth of the emitter region;

a depth of a second portion of the first region underlying the emitter region is greater than or equal to the depth of the collector region;

a distance between a lateral boundary of the base well region and a proximal lateral boundary of the collector region is greater than zero; and

the portion of the first region resides between the collector region and the base well region.

4. The semiconductor device of claim 1 , wherein:

the first region and the emitter region are coupled to a first terminal; and

the collector region is coupled to a second terminal.

5. The semiconductor device of claim 1 , wherein a distance between a lateral boundary of the emitter region and a proximal lateral boundary of the collector region is greater than zero.

6. The semiconductor device of claim 1 , wherein the collector region does not extend laterally underneath the emitter region.

7. The semiconductor device of claim 1 , wherein the collector region contacts an underlying layer of dielectric material.

8. The semiconductor device of claim 7 , wherein the second portion abuts the underlying layer of dielectric material.

9. The semiconductor device of claim 1 , further comprising:

an isolation region within the first region, wherein:

the isolation region resides laterally between the base contact region and the emitter region; and

the base contact region and the emitter region are electrically connected.

10. The semiconductor device of claim 1 , further comprising:

a first interface;

a second interface; and

functional circuitry coupled between the first interface and the second interface, wherein:

the base contact region and the emitter region are coupled to the first interface; and

the collector region is coupled to the second interface.

11. The semiconductor device of claim 1 , further comprising an isolation region within the base well region, wherein:

the isolation region resides laterally between the base contact region and the emitter region; and

the base contact region and the emitter region are electrically connected.

12. The semiconductor device of claim 2 , wherein the buried region does not extend laterally underneath the emitter region.

13. The semiconductor device of claim 2 , wherein lateral boundaries of the well region are substantially aligned with lateral boundaries of the buried region.

14. The semiconductor device of claim 1 , further comprising:

a second region of semiconductor material having the first conductivity type; and

a second emitter region of semiconductor material having the second conductivity type, wherein:

a third portion of the second region resides between the second emitter region and the collector region;

the depth of the collector region is greater than a depth of the second emitter region; and

a depth of the second region is greater than or equal to the depth of the collector region.

15. The semiconductor device of claim 14 , wherein:

the first region, the emitter region, the second region, and the second emitter region are coupled to a first terminal; and

the collector region is coupled to a second terminal.

16. The semiconductor device of claim 14 , further comprising:

a third emitter region of semiconductor material having the second conductivity type; and

a second collector region of semiconductor material having the second conductivity type, wherein:

a fourth portion of the second region resides between the third emitter region and the second collector region;

a depth of the second collector region is greater than a depth of the third emitter region; and

the depth of the second region is greater than or equal to a depth of the second collector region.

17. The semiconductor device of claim 2 , wherein the base contact region and the emitter region are electrically connected.

18. The semiconductor device of claim 17 , further comprising:

a first interface;

a second interface; and

functional circuitry coupled between the first interface and the second interface, wherein:

the base contact region and the emitter region are coupled to the first interface; and

the collector region is coupled to the second interface.

19. The semiconductor device of claim 2 , wherein:

the first region and the emitter region are coupled to a first terminal; and

the collector region is coupled to a second terminal.

20. The semiconductor device of claim 2 , wherein a distance between a lateral boundary of the emitter region and a proximal lateral boundary of the collector region is greater than zero.

Assignments (20)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050744/0097 →
CORRECTIVE ASSIGNMENT TO CORRECT THE TO CORRECT THE APPLICATION NO. FROM 13,883,290 TO 13,833,290 PREVIOUSLY RECORDED ON REEL 041703 FRAME 0536. ASSIGNOR(S) HEREBY CONFIRMS THE THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS.. Recorded Feb 20, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: SHENZHEN XINGUODU TECHNOLOGY CO., LTD.
Reel/Frame 048734/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE PATENTS 8108266 AND 8062324 AND REPLACE THEM WITH 6108266 AND 8060324 PREVIOUSLY RECORDED ON REEL 037518 FRAME 0292. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Feb 1, 2017
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 041703/0536 →
CORRECTIVE ASSIGNMENT TO CORRECT THE NATURE OF CONVEYANCE PREVIOUSLY RECORDED AT REEL: 040626 FRAME: 0683. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER AND CHANGE OF NAME EFFECTIVE NOVEMBER 7, 2016. Recorded Jan 12, 2017
From: NXP SEMICONDUCTORS USA, INC. (MERGED INTO); FREESCALE SEMICONDUCTOR, INC. (UNDER)
To: NXP USA, INC.
Reel/Frame 041414/0883 →
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNMENT DOCUMENTATION - INITIAL CONVENYANCE LISTED CHANGE OF NAME. PREVIOUSLY RECORDED ON REEL 040579 FRAME 0827. ASSIGNOR(S) HEREBY CONFIRMS THE UPDATE CONVEYANCE TO MERGER AND CHANGE OF NAME EFFECTIVE NOVEMBER 7, 2016. Recorded Dec 15, 2016
From: NXP SEMICONDUCTORS USA, INC. (MERGED INTO); FREESCALE SEMICONDUCTOR, INC. (UNDER)
To: NXP USA, INC.
Reel/Frame 040945/0252 →
CHANGE OF NAME Recorded Nov 16, 2016
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
Reel/Frame 040626/0683 →
CHANGE OF NAME Recorded Nov 9, 2016
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
Reel/Frame 040579/0827 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE INCORRECT PCT NUMBERS IB2013000664, US2013051970, US201305935 PREVIOUSLY RECORDED AT REEL: 037444 FRAME: 0787. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Oct 17, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 040450/0715 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →
SUPPLEMENT TO THE SECURITY AGREEMENT Recorded Jun 16, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039138/0001 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 13, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
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ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 5, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037444/0787 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0874 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Nov 13, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS COLLATERAL AGENT
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SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Nov 13, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
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SECURITY AGREEMENT Recorded Nov 6, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
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ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 26, 2013
From: CHEN, WEN-YI; GILL, CHAI EAN
To: FREESCALE SEMICONDUCTOR INC.
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