Non-volatile memory (NVM) cell and high-K and metal gate transistor integration
View Patent ↗A method of making a semiconductor device includes depositing a layer of polysilicon in a non-volatile memory (NVM) region and a logic region of a substrate. The layer of polysilicon is patterned into a gate in the NVM region while the layer of polysilicon remains in the logic region. A memory cell is formed including the gate in the NVM region while the layer of polysilicon remains in the logic region. The layer of polysilicon in the logic region is removed and the substrate is implanted to form a well region in the logic region after the memory cell is formed. A layer of gate material is deposited in the logic region. The layer of gate material is patterned into a logic gate in the logic region.
1. A method of making a semiconductor device comprising:
depositing a layer of polysilicon in a non-volatile memory (NVM) region and a logic region of a substrate;
patterning the layer of polysilicon into a gate in the NVM region while the layer of polysilicon remains in the logic region;
forming a memory cell including the gate in the NVM region while the layer of polysilicon remains in the logic region;
removing the layer of polysilicon in the logic region;
implanting the substrate to form a well region in the logic region after the forming the memory cell;
depositing a layer of gate material in the logic region; and
patterning the layer of gate material into a logic gate in the logic region.
2. The method of claim 1 , wherein the gate in the NVM region is a select gate, the forming the memory cell comprising:
forming a charge storage layer over the select gate and over the logic region;
depositing a second polysilicon layer over the charge storage layer;
patterning the second polysilicon layer to form a control gate over a portion of a top and sidewall of the select gate; and
removing the charge storage layer from areas of the NVM region that do not underlie the control gate and from the logic region.
3. The method of claim 2 wherein the charge storage layer includes at least one of a group consisting of: nanocrystals between layers of dielectric material, a layer that includes silicon nitride, a continuous conductive layer between layers of dielectric material, and a layer of polysilicon between layers of dielectric material.
4. The method of claim 1 further comprising forming a logic transistor including the logic gate.
5. The method of claim 1 wherein the substrate further includes a high-voltage region, the method further comprising:
implanting the substrate to form a well region in a high voltage region after the patterning the layer of polysilicon into the gate in the NVM region;
depositing the layer of gate material in the high-voltage region;
patterning the layer of gate material into a gate in the high-voltage region; and
forming a high voltage transistor including the gate in the high voltage region.
6. The method of claim 5 further comprising:
forming an oxide layer in the high voltage region while the layer of polysilicon remains in the logic region.
7. The method of claim 6 wherein the oxide layer in the high voltage region is a grown thermal oxide.
8. The method of claim 4 further comprising:
forming first spacers on the memory cell and the logic gate; and
after forming the first spacers, creating doped implant regions in the substrate for the memory cell and the logic transistor.
9. The method of claim 8 further comprising:
after creating the doped implant regions, forming self-aligned silicide regions on exposed portions of the doped implant regions.
10. The method of claim 1 further comprising:
depositing a protection layer in the logic region and the NVM region;
removing the protection layer from the logic region; and
depositing a high-k dielectric layer over the logic region and the NVM region after the removing the protection layer from the logic region.
11. The method of claim 8 , wherein the logic gate is a sacrificial gate, the method further comprising:
removing the sacrificial gate in the logic region after the forming the first spacers; and
forming a metal gate between the first spacers in the logic region.
12. The method of claim 2 further comprising:
creating doped implant regions in the control gate, the select gate, and the logic gate.
13. A method of making a semiconductor device comprising:
depositing a polysilicon layer over a non-volatile memory (NVM) region and a logic region of a substrate;
forming a split gate memory cell in the NVM region of a substrate using a first portion of the polysilicon layer as a select gate in the split gate memory cell while a second portion of the polysilicon layer remains in the logic region;
after the forming the split gate memory cell, removing the second portion of the polysilicon layer;
creating a doped well in the logic region after the second portion of the polysilicon layer is removed; and
forming a logic transistor in the logic region after creating the doped well in the logic region.
14. The method of claim 13 further comprising:
depositing the polysilicon layer over a high voltage region of the substrate;
removing a third portion of the polysilicon layer in the high voltage region while forming the split gate memory cell in the NVM region;
implanting the substrate to form a well region in the high voltage region after forming the select gate in the NVM region;
forming a protection layer over the split gate memory cell in the NVM region;
forming an oxide layer in the high voltage region while the polysilicon layer remains in the logic region and the protection layer remains over the split gate memory cell;
depositing a layer of gate material in the high-voltage region and the logic region;
patterning the layer of gate material into a gate in the high voltage region; and
forming a high voltage transistor including the gate in the high voltage region.
15. The method of claim 13 wherein the logic transistor is a high-k metal gate transistor.
16. The method of claim 13 further comprising:
depositing a protection layer over the split gate memory cell before creating the doped well in the logic region.
17. The method of claim 13 wherein the forming the split gate memory cell comprises:
forming the select gate;
forming a charge storage layer over the select gate; and
forming a control gate over the charge storage layer.
18. The method of claim 13 wherein the forming the logic transistor comprises:
removing a sacrificial gate in the logic region after forming first spacers on the sacrificial gate; and
forming a metal gate between the first spacers in the logic region.
19. A method of making a semiconductor device comprising:
forming a non-volatile memory (NVM) cell in a memory region of a substrate,
wherein forming the NVM cell includes:
depositing polysilicon over the memory region and a logic region of the substrate; and
forming a gate for the NVM cell using a first portion of the polysilicon while a second portion of the polysilicon remains in the logic region;
forming a protection layer on the NVM cell;
removing the second portion of the polysilicon after the forming the protection layer;
doping the substrate to form a well in the logic region after the removing the second portion of the polysilicon;
forming a logic gate stack in the logic region, the logic gate stack including a high-k dielectric material; and
forming a logic transistor including the logic gate stack.
20. The method of claim 19 further comprising:
implanting the substrate to form a well region in a high voltage region of the substrate after the forming the gate for the NVM cell;
forming a high-voltage gate stack in the high-voltage region, the high voltage gate stack including the high-k dielectric material; and
forming a high voltage transistor including the high voltage gate stack.