Modular gray code counter
View Patent ↗A Gray code counter has multiple two-bit Gray code counter modules, clock gated integrated cells (CGICs), and a parity bit generator. The CGICs gate clock signals provided to the two-bit counter modules, which reduces dynamic power consumption. The parity bit generator generates a parity bit that indicates a count of binary ones in a counting state.
1. A Gray code counter circuit, comprising:
a first counter circuit ( 216 ) for receiving a first direction bit and a first gated clock signal and generating zeroth and first Gray code bits;
a first AND gate ( 228 ) for receiving an inverted zeroth Gray code bit and a parity bit and generating a first enable signal;
a first NOT gate ( 222 ) connected to an output terminal of the first AND gate for receiving the first enable signal and generating an inverted first enable signal;
a first Clock Gating Integrated Cell (CGIC) ( 206 ) connected to the first NOT gate for receiving the inverted first enable signal, and a clock signal, and generating the first gated clock signal;
a second CGIC ( 208 ) connected to the output terminal of the first AND gate for receiving the first enable signal, and the clock signal, and generating a second gated clock signal;
a first flip-flop ( 202 ) that receives an inverted first direction bit at a data input terminal, and the second gated clock signal at a clock input terminal, and generates the first direction bit;
a second NOT gate ( 224 ) connected to the output terminal of the first flip-flop for receiving the first direction bit, and providing the inverted first direction bit to the first flip-flop;
a first OR gate ( 234 ) for receiving the first Gray code bit and a second Gray code bit and generating a first intermediate signal;
a second AND gate ( 230 ), connected to the output terminal of the first AND gate for receiving the first enable signal and to an output terminal of the first OR gate for receiving the first intermediate signal, for generating a second enable signal;
a third CGIC ( 210 ), connected to the output terminal of the second AND gate for receiving the second enable signal, and the clock signal, for generating a third gated clock signal;
a second counter circuit ( 218 ) that receives a second direction bit and the third gated clock signal, and generates the second Gray code bit and a third Gray code bit;
a fourth CGIC ( 212 ) for receiving a third enable signal and the clock signal and generating a fourth gated clock signal;
a second flip-flop ( 204 ) that receives an inverted second direction bit at its data input terminal and the fourth gated clock signal at its clock input terminal, and generates the second direction bit;
a third NOT gate ( 226 ) that receives the second direction bit and generates the inverted second direction bit;
a NOR gate ( 236 ) for receiving the zeroth, first and second Gray code bits and generates a second intermediate signal;
a third AND gate ( 232 ) that receives the second intermediate signal and the parity bit, and generates the third enable signal;
a fifth CGIC ( 214 ) that receives the third enable signal and the clock signal, and generates a fifth gated clock signal; and
a third counter circuit ( 220 ) for receiving a third direction bit and the fifth gated clock signal, and generating fourth and fifth Gray code bits.
2. The Gray code counter circuit of claim 1 , wherein the third direction bit is binary zero.
3. The Gray code counter circuit of claim 1 , wherein the first counter circuit includes:
a XOR gate ( 102 ) that receives the first direction bit and the zeroth Gray code bit and generates a third intermediate signal;
a third flip-flop ( 104 ) having a data input terminal connected to an output terminal of the XOR gate for receiving the third intermediate signal, and a clock input terminal connected to the first CGIC for receiving the first gated clock signal, wherein the third flip-flop generates the first Gray code bit at an output terminal thereof;
a XNOR gate ( 110 ) for receiving the first direction bit and the first Gray code bit and generating a fourth intermediate signal;
a fourth AND gate ( 112 ) that receives inverted zeroth and first Gray code bits and generates a fifth intermediate signal;
a second OR gate ( 108 ) that receives the fourth and fifth intermediate signals and generates a sixth intermediate signal; and
a fourth flip-flop ( 106 ) that receives the sixth intermediate signal at its data input terminal and the first gated clock signal at its clock input terminal and generates the zeroth Gray code bit.
4. The Gray code counter circuit of claim 3 , wherein the first CGIC includes:
a latch ( 118 ) having a data input terminal that receives the inverted first enable signal, and a clock input terminal that receives an inverted clock signal, and a data output terminal that provides a seventh intermediate signal; and
a fifth AND gate ( 120 ) that receives the seventh intermediate signal and the clock signal and generates the first gated clock signal.
5. The Gray code counter circuit of claim 1 , wherein the parity bit is generated using a parity bit generator.
6. The Gray code counter circuit of claim 5 , wherein the parity bit generator comprises:
a fifth flip-flop ( 124 ) having a data input terminal for receiving an inverted parity bit, and a clock input terminal for receiving the clock signal, and an output terminal for providing the parity bit; and
a fourth NOT gate ( 122 ) connected to the output terminal of the fifth flip-flop for receiving the parity bit and generating the inverted parity bit.