Granted Patent B2

US 9,368,162 · App. 13/983,145 · Granted Jun 14, 2016

Abstract

Claims (35)

1. An integrated circuit device comprising:

a central processing unit (CPU);

at least one on-die buffer memory module operably coupled to the CPU, the at least one on-die buffer memory module comprising a plurality of memory sub-modules; and

at least one power management module operably coupled to the on-die buffer memory module and configured to provide power management for the at least one on-die buffer memory module when the CPU is inactive;

wherein the at least one power management module is configured to:

dynamically determine when content of at least one memory sub-module has become redundant; and

place the at least one memory sub-module into a powered-down state upon determining that content of the at least one memory sub-module is redundant.

2. The integrated circuit device of claim 1 further comprising:

an on-die dual data rate (DDR) controller operably coupled to the CPU, wherein the at least one power management module is further configured to provide power management for the at least one on-die buffer memory module when the on-die DDR controller is inactive.

3. The integrated circuit device of claim 1 further comprising:

an on-die memory controller operably coupled to the at least one on-die buffer memory module and to the DDR controller, wherein the on-die memory controller is configured to control access to the at least one on-die buffer memory module.

4. The integrated circuit device of claim 1 further comprising:

an on-die direct memory access (DMA) module operably coupled to the CPU, wherein the at least one power management module is further configured to provide power management for the at least one on-die buffer memory module when the on-die DMA module is active.

5. The integrated circuit device of claim 4 further comprising:

an on-die synchronous serial interface (SSI) operably coupled to the CPU, wherein the at least one power management module is further configured to provide power management for the at least one on-die buffer memory module when the on-die SSI is active.

6. The integrated circuit device of claim 1 , wherein the at least one power management module is further configured to restore power to the CPU for more data to be loaded into the at least one on-die buffer memory module.

7. The integrated circuit device of claim 1 , wherein the at least one power management module is further configured to provide independent power control for each of a plurality of a plurality of sub-modules the at least one on-die buffer memory module.

8. A power management module configured to provide power management for at least one on-die buffer memory module comprising a plurality of memory sub-modules when an on-die central processing unit (CPU) is inactive; the power management module being configured to:

dynamically determine when content of at least one memory sub-module has become redundant; and

place the at least one memory sub-module into a powered-down state upon determining that content of the at least one memory sub-module is redundant.

9. The power management module of claim 8 further configured to provide power management for the at least one on-die buffer memory module when an on-die dual data rate (DDR) controller is inactive.

10. The power management module of claim 8 wherein access to the at least one on-die buffer memory module is configured to be controlled by an on-die memory controller.

11. The power management module of claim 8 , wherein the power management module is further configured to provide power management for the at least one on-die buffer memory module when an on-die direct memory access (DMA) module is active.

12. The power management module of claim 8 , wherein the power management module is further configured to provide power management for the at least one on-die buffer memory module when an on-die synchronous serial interface (SSI) is active.

13. The power management module of claim 8 , wherein the power management module is further configured to restore power to the CPU for more data to be loaded into the at least one on-die buffer memory module.

14. The power management module of claim 8 , wherein the power management module is further configured to provide independent power control for each of a plurality of sub-modules of the at least one on-die buffer memory module.

15. A method for providing power management to at least one on-die buffer memory module when an on-die central processing unit (CPU) is inactive, the method comprising:

dynamically determining when content of at least one memory sub-module of the on-die buffer memory module has become redundant; and

placing the at least one memory sub-module into a powered-down state, upon determining that content of the at least one memory sub-module is redundant.

16. The method of claim 15 , wherein the method is further for providing power management to at least one on-die buffer memory module when an on-die dual data rate (DDR) controller is inactive.

17. The method of claim 15 , wherein the method is further for providing power management to at least one on-die buffer memory module when an on-die direct memory access (DMA) module is active.

18. The method of claim 15 , wherein the method is further for providing power management to at least one on-die buffer memory module when an on-die synchronous serial interface (SSI) is active.

19. The method of claim 15 , wherein the method further comprises:

restoring power to the CPU for more data to be loaded into the at least one on-die buffer memory module.

20. The method of claim 15 , wherein the power management is provided independently for each of a plurality of sub-modules of the at least one on-die buffer memory module.

Assignments (28)