Edge coupling of semiconductor dies
View Patent ↗Edge coupling of semiconductor dies. In some embodiments, a semiconductor device may include a first semiconductor die, a second semiconductor die disposed in a face-to-face configuration with respect to the first semiconductor die, and an interposer arranged between the first semiconductor and second semiconductor dies, the interposer having an edge detent configured to allow an electrical coupling between the first and second semiconductor dies. In other embodiments, a method may include coupling a first semiconductor die to a surface of an interposer where an edge of the interposer includes detents and the first semiconductor die includes a first pad aligned with a first detent, coupling a second semiconductor die to an opposite surface of the interposer where the first and second semiconductor dies are in a face-to-face configuration and the second semiconductor die includes a second pad aligned with a second detent, and coupling the first and second pads together.
1. A semiconductor device, comprising:
a first semiconductor die;
a second semiconductor die disposed in a face-to-face configuration with respect to the first semiconductor die; and
an interposer sandwiched between a first adhesive layer disposed on a bottom surface of the first semiconductor die and a second adhesive layer disposed on a top surface of the second semiconductor die, wherein the interposer has having an edge detent located at an outermost perimeter of the interposer, wherein the first adhesive layer is separated from a first pad on the bottom surface of the first semiconductor die by a first passivation component, wherein the second adhesive layer is separated from a second pad on the bottom surface of the second semiconductor die by a second passivation component, and wherein the edge detent is configured to receive a solder ball to allow an electrical coupling between corresponding electrical terminals on the first and second semiconductor dies without the use of bondwires between the corresponding electrical terminals.
2. The semiconductor device of claim 1 , wherein the edge detent is aligned with respect to the first pad of the first semiconductor die and to the second pad of the second semiconductor die.
3. The semiconductor device of claim 2 , wherein the first semiconductor die includes a redistribution bus configured to couple the first pad to a pad at a location corresponding to the second pad of the second semiconductor die.
4. The semiconductor device of claim 3 , wherein the given location is a mirror image of the original location.
5. The semiconductor device of claim 3 , wherein the redistribution bus is configured to conduct at least one power signal, at least one clock signal, at least one memory read signal, or at least one memory write signal.
6. The semiconductor device of claim 1 , wherein the first semiconductor die and the second semiconductor die have the same topology.
7. The semiconductor device of claim 1 , wherein the interposer is a passive interposer including silicon, glass, or ceramic.
8. The semiconductor device of claim 1 , wherein the interposer includes a lead frame configured to couple the first pad to a pad at a different location of the first semiconductor die.
9. A semiconductor device, comprising:
a first module including:
a first semiconductor die;
a second semiconductor die disposed in a face-to-face configuration with respect to the first semiconductor die; and
a first interposer sandwiched between a first adhesive layer disposed on a bottom surface of the first semiconductor die and a second adhesive layer disposed on a top surface of the second semiconductor die, wherein the first interposer has one or more detents along the outermost perimeter of the first interposer, wherein the first adhesive layer is separated from a first pad on the bottom surface of the first semiconductor die by a first passivation component, wherein the second adhesive layer is separated from a second pad on the bottom surface of the second semiconductor die by a second passivation component, and wherein each detent is configured receive a solder ball to allow an electrical coupling between corresponding electrical terminals on the first and second semiconductor dies without the use of bondwires between the corresponding electrical terminals; and
a second module coupled to the first module, the second module including:
a third semiconductor die;
a fourth semiconductor die disposed in a face-to-face configuration with respect to the third semiconductor die; and
a second interposer sandwiched between the third semiconductor die and the fourth semiconductor die, the second interposer having one or more detents along the outermost perimeter of the second interposer, each detent configured to allow an electrical coupling between the third and fourth semiconductor dies.
10. The semiconductor device of claim 9 , wherein the second module is coupled to the first module in a side-by-side configuration such that a first pad on the first semiconductor die, a second pad on the second semiconductor die, a third pad on the third semiconductor die, and a fourth pad on the fourth semiconductor die are coupled together directly via the solder ball without the use of bondwires.
11. The semiconductor device of claim 9 , wherein the second module is stacked over the first module, wherein the first and second modules are coupled to a backplane, and wherein the backplane includes a bus configured to couple, via the solder ball and without the use of bondwires: (i) a first pad on the first semiconductor die and a second pad on the second semiconductor die to (ii) a third pad on the third semiconductor die and a fourth pad on the fourth semiconductor die.