Granted Patent B2

US 9,088,941 · App. 13/938,248 · Granted Jul 21, 2015

Abstract

Claims (35)

1. An transmission node for use in a chain in a wireless communication network, comprising:

a first Common Public Radio Interface (CPRI) unit comprising a first auxiliary interface for transmitting auxiliary data to a second CPRI unit in the transmission node, wherein the auxiliary data comprises control word data and IQ data;

a memory unit for storing the control word data;

a memory write block connected between the first auxiliary interface and the memory unit for writing the control word data to the memory unit based on a first set of frame timing signals received from the first auxiliary interface; and

a memory read and merge block connected to the memory unit for reading the control word data stored in the memory unit based on a second set of frame timing signals, and merging the control word data with the IQ data from the first auxiliary interface,

wherein the second CPRI unit comprises a second auxiliary interface connected to the memory read and merge block for receiving the merged auxiliary data, and

wherein the memory read and merge block comprises:

a memory read interface connected to the memory unit for reading the control word data stored in the memory unit based on a memory read signal;

a merge logic unit connected to the memory read interface and the first auxiliary interface for merging the control word data received from the memory read interface with the IQ data transmitted from the first auxiliary interface; and

a second timing and management logic unit connected between the second auxiliary interface and the memory read interface for generating the memory read signal based on the second set of frame timing signals received from the second auxiliary interface.

2. The transmission node of claim 1 , wherein the memory write block comprises:

a memory write interface connected between the first auxiliary interface and the memory unit for writing the control word data to the memory unit based on a memory write signal; and

a first timing and management logic unit connected between the first auxiliary interface and the memory write interface for receiving the first set of frame timing signals and generating the memory write signal based on the first set of frame timing signals.

3. The transmission node of claim 2 , wherein the first set of frame timing signals comprises:

a first synchronization status signal for indicating that the first CPRI unit has synchronized up to a downlink node in the chain; and

a first segment number for detecting the control word data in the auxiliary data in the first CPRI unit.

4. The transmission node of claim 3 , wherein the first timing and management logic unit instructs the memory write interface to write the control data to the memory unit with the memory write signal when the first CPRI unit has synchronized with the downlink node in the chain, and the control word data in the auxiliary data has been detected.

5. The transmission node of claim 1 , wherein the second set of frame timing signals comprises:

a second synchronization status signal for indicating that the second CPRI unit has synchronized with an uplink node in the chain; and

a second segment number for detecting the control word data in the auxiliary data.

6. The transmission node of claim 5 , wherein the second timing and management logic unit instructs the memory read interface to read the control data from the memory unit with the memory read signal when the second CPRI unit has synchronized with the uplink node in the chain, and the control data in the auxiliary data has been detected.

7. The transmission node of claim 1 , wherein the memory unit comprises a plurality of registers arranged as a dual port FIFO stack.

8. A method of operating a transmission node for use in a chain in a wireless communication network, comprising:

writing control word data in auxiliary data transmitted from a first auxiliary interface of a first Common Public Radio Interface (CPRI) unit to a memory unit based on a first set of frame timing signals received from the first auxiliary interface, wherein the auxiliary data comprises the control word data and IQ data;

reading the control word data stored in the memory unit based on a second set of frame timing signals received from a second auxiliary interface of a second CPRI unit in the transmission node;

merging the control word data read from the memory unit with the IQ data received from the first auxiliary interface; and

transmitting the merged auxiliary data to the second auxiliary interface, wherein a memory read signal is generated based on the second set of frame timing signals to instruct reading the control word data from the memory unit.

9. The method of claim 8 , wherein a memory write signal is generated based on the first set of frame timing signals to instruct writing the control word data to the memory unit.

10. The method of claim 9 , wherein the first set of frame timing signals comprises:

a first synchronization status signal for indicating that the first CPRI unit has synchronized up to a downlink node in the chain; and

a first segment number for detecting the control word data in the auxiliary data, wherein the memory write signal is generated when the first CPRI unit has synchronized up to the downlink node in the chain, and the control word data in the auxiliary data has been detected.

11. The method of claim 8 , wherein the second set of frame timing signals comprises:

a second synchronization status signal for indicating that the second CPRI unit has synchronized to an uplink node in the chain; and

a second segment number for detecting the control word data in the auxiliary data, wherein the memory read signal is generated when the second CPRI unit has synchronized to the uplink node in the chain, and the control data in the auxiliary data has been detected.

12. The method of claim 8 , wherein the memory unit comprises a plurality of registers arranged as a dual port FIFO stack.

Assignments (19)