Split-gate non-volatile memory (NVM) cell and device structure integration
View Patent ↗A method includes forming a first conductive layer over a substrate in a first region and second region of the substrate; patterning the first conductive layer to form a select gate in the first region and to remove the first conductive layer from the second region; forming a charge storage layer over the select gate and the substrate in the first region and over the substrate in the second region; forming a second conductive layer over the charge storage layer in the first and second regions; and patterning the second conductive layer and charge storage layer to form a control gate overlapping the select gate in the first region, wherein a first portion of the charge storage layer remains between the select gate and control gate, and to form an electrode in the second region, wherein a second portion of the charge storage layer remains between the electrode and substrate.
1. A method for forming a semiconductor structure, the method comprising:
forming a first conductive layer over a substrate in a first region and a second region of the substrate;
patterning the first conductive layer to form a select gate in the first region and to remove the first conductive layer from the second region;
forming a charge storage layer over the select gate and the substrate in the first region and over the substrate in the second region;
forming a second conductive layer over the charge storage layer in the first region and the second region; and
patterning the second conductive layer and the charge storage layer to form a control gate overlapping the select gate in the first region, wherein a first portion of the charge storage layer remains between the select gate and the control gate, and to form an electrode in the second region, wherein a second portion of the charge storage layer remains between the electrode and the substrate.
2. The method of claim 1 , wherein the electrode is further characterized as an electrode of a capacitor.
3. The method of claim 1 , wherein the electrode is further characterized as a gate of a transistor.
4. The method of claim 1 , wherein the electrode is further characterized as a gate of a memory cell.
5. The method of claim 1 , further comprising:
forming a first source drain region in the substrate adjacent a sidewall of the select gate; and
forming a second source/drain region in the substrate adjacent a first sidewall of the control gate.
6. The method of claim 5 , further comprising:
forming a sidewall spacer over the substrate and adjacent the sidewall of the select gate, over the substrate and adjacent the first sidewall of the control gate, and over the select gate and adjacent a second sidewall of the control gate.
7. The method of claim 5 , further comprising:
forming a third source/drain region in the substrate adjacent a first sidewall of the electrode; and
forming a fourth source/drain region in the substrate adjacent a second sidewall of the electrode.
8. The method of claim 7 , further comprising:
forming a sidewall spacer adjacent the first and second sidewalls of the electrode.
9. The method of claim 1 , wherein the control gate, the first portion of the charge storage layer, and the select gate are further characterized as a portion of a memory device.
10. The method of claim 1 , wherein the forming the charge storage layer comprises:
forming a plurality of nanocrystals over the select gate and the substrate in the first region and over the substrate in the second region; and
forming a dielectric layer over the plurality of nanocrystals.
11. The method of claim 1 , further comprising:
prior to forming the first conductive layer over the substrate, forming a first well in the substrate in the first region and forming a second well in the substrate in the second region, wherein the select gate and the control gate over formed over the first well, and the electrode is formed over the second well.
12. A method for forming a semiconductor structure, the method comprising:
forming a first conductive layer over a substrate in a first region and a second region of the substrate;
forming a select gate from the first conductive layer in the first region;
removing the first conductive layer from the second region;
forming a charge storage layer over the select gate and the substrate in the first region and over the substrate in the second region;
forming a second conductive layer over the charge storage layer in the first region and the second region;
patterning the second conductive layer and the charge storage layer to form a control gate from the second conductive layer overlapping the select gate in the first region, wherein a first portion of the charge storage layer remains between the select gate and the control gate, and to form a capacitor electrode from the second conductive layer in the second region, wherein a second portion of the charge storage layer remains between the capacitor electrode and the substrate and the second portion of the charge storage layer is further characterized as a capacitor dielectric; and
forming a first source drain region in the substrate adjacent a sidewall of the select gate and a second source/drain region in the substrate adjacent a first sidewall of the control gate.
13. The method of claim 12 , further comprising:
forming a third source/drain region in the substrate adjacent a first sidewall of the capacitor electrode; and
forming a fourth source/drain region in the substrate adjacent a second sidewall of the capacitor electrode.
14. The method of claim 13 , further comprising:
forming a sidewall spacer adjacent the first and second sidewalls of the capacitor electrode.
15. The method of claim 12 , further comprising:
forming a sidewall spacer over the substrate and adjacent the sidewall of the select gate, over the substrate and adjacent the first sidewall of the control gate, and over the select gate and adjacent a second sidewall of the control gate.
16. The method of claim 12 , wherein the forming the charge storage layer comprises:
forming a plurality of nanocrystals over the select gate and the substrate in the first region and over the substrate in the second region; and
forming a dielectric layer over the plurality of nanocrystals.