Power switch with current limitation and zero direct current (DC) power consumption
View Patent ↗Power switches with current limitation and zero Direct Current (DC) power consumption. In an embodiment, an integrated circuit includes switching circuitry coupled between a voltage supply node and a given one of a plurality of power domains, the switching circuitry configured to limit an amount of current drawn by the given power domain from the voltage supply node during a transition period, the switching circuitry further configured to consume zero DC power outside of the transition period. In another embodiment, a method includes controlling, via a switching circuit coupled between a voltage supply and an integrated circuit, an amount of current drawn by the integrated circuit from the voltage supply during a transition period; and causing the switching circuit to consume no static power during periods of time other than the transition period.
1. An electronic device, comprising:
a power supply;
an integrated circuit including a plurality of power domains; and
a switching circuit coupled between the power supply and a given one of the plurality of power domains, the switching circuit including:
a first current mirror including a first transistor and a second transistor, the first transistor including a first current terminal coupled to the voltage supply node, the first transistor including a second current terminal coupled to the given one of the plurality of power domains, the second transistor including a first current terminal coupled to the first current terminal of the first transistor, and the second transistor including a control terminal coupled to a control terminal of the first transistor; and
a second current mirror including a third transistor and a fourth transistor, the third transistor including a first current terminal coupled to a second current terminal of the second transistor, the third transistor including a second control terminal coupled to a first current source and to the control terminals of the first and second transistors, the fourth transistor including a first current terminal coupled to the second current terminal of the first transistor, the fourth transistor including a second current terminal coupled to a second current source, and the fourth transistor including a control terminal coupled to a control terminal of the third transistor and to the second current terminal of the fourth transistor;
wherein the switching circuit is configured to limit an amount of current drawn by the given one of the plurality of power domains from the power supply during a transition period, the switching circuit further configured to consume zero Direct Current (DC) power outside of the transition period, and wherein the switching circuit further comprises a fifth transistor including a first current terminal coupled to the first current terminal of the fourth transistor, a control terminal coupled to the control terminals of the first and second transistors, and a second current terminal coupled to a third current source, the second current terminal of the fifth transistor configured to provide a signal indicative of whether the transition period has ended.
2. The electronic device of claim 1 , wherein the first, second, third, and fourth transistors are P-type Metal-Oxide-Semiconductor (PMOS) transistors.
3. The electronic device of claim 1 , wherein a difference between voltages at the first and second current terminals of the first transistor determines whether the second transistor operates in saturation, triode, or linear mode.
4. The electronic device of claim 1 , the switching circuit further comprising a sixth transistor coupled to the control terminal of the first and second transistors and to the second current terminal of the third transistor.
5. The electronic device of claim 4 , further comprising a logic circuit coupled the switching circuit, the logic circuit configured to reconfigure the switching circuit in response to a determination that a voltage drop across the switching circuit is below a threshold value.
6. The electronic device of claim 5 , wherein reconfiguring the switching circuit includes turning off the first, second, and third current sources, and making the sixth transistor conductive.
7. The electronic device of claim 1 , wherein the transition period includes powering up of the given one of the plurality of power domains.
8. The electronic device of claim 1 , wherein the transition period lasts 30 μs or less.
9. The electronic device of claim 1 , wherein the limit is proportional to an aspect ratio of the first transistor divided by an aspect ratio of the second transistor.
10. The electronic device of claim 1 , wherein an aspect ratio of the fourth transistor is greater than an aspect ratio of the third transistor.
11. A method, comprising:
controlling, via a switching circuit coupled between a voltage supply and an integrated circuit including a plurality of power domains, an amount of current drawn by the integrated circuit from the voltage supply during a transition period, the switching circuit further comprising:
a first current mirror including a first transistor and a second transistor, the first transistor including a first current terminal coupled to the voltage supply, the first transistor including a second current terminal coupled to a given one of the plurality of power domains, the second transistor including a first current terminal coupled to the first current terminal of the first transistor, and the second transistor including a control terminal coupled to a control terminal of the first transistor; and
a second current mirror including a third transistor and a fourth transistor, the third transistor including a first current terminal coupled to a second current terminal of the second transistor, the third transistor including a second control terminal coupled to a first current source and to the control terminals of the first and second transistors, the fourth transistor including a first current terminal coupled to the second current terminal of the first transistor, the fourth transistor including a second current terminal coupled to a second current source, and the fourth transistor including a control terminal coupled to a control terminal of the third transistor and to the second current terminal of the fourth transistor; wherein the switching circuit is configured to limit an amount of current drawn by the given one of the plurality of power domains from the power supply during a transition period, the switching circuit further configured to consume zero Direct Current (DC) power outside of the transition period, and wherein the switching circuit further comprises a fifth transistor including a first current terminal coupled to the first current terminal of the fourth transistor, a control terminal coupled to the control terminals of the first and second transistors, and a second current terminal coupled to a third current source, the second current terminal of the fifth transistor configured to provide a signal indicative of whether the transition period has ended; and
causing the switching circuit to consume no static power during periods of time other than the transition period.
12. The method of claim 11 , wherein the integrated circuit is one of a plurality of different power domains within another integrated circuit.
13. The method of claim 11 , wherein the transition period includes a powering up of the integrated circuit.
14. The method of claim 13 , wherein the transition period is 30 μs or less.
15. The method of claim 11 , wherein causing the switching circuit to consume no static power includes decoupling the switching circuit from a ground node in response to a determination that the transition period has ended.
16. An integrated circuit, comprising:
switching circuitry coupled between a voltage supply node and a given one of a plurality of power domains, the switching circuitry configured to limit an amount of current drawn by the given power domain from the voltage supply node during a transition period, the switching circuitry further configured to consume zero Direct Current (DC) power outside of the transition period, the switching circuit further comprising:
a first current mirror including a first transistor and a second transistor, the first transistor including a first current terminal coupled to the voltage supply node, the first transistor including a second current terminal coupled to the given one of the plurality of power domains, the second transistor including a first current terminal coupled to the first current terminal of the first transistor, and the second transistor including a control terminal coupled to a control terminal of the first transistor; and
a second current mirror including a third transistor and a fourth transistor, the third transistor including a first current terminal coupled to a second current terminal of the second transistor, the third transistor including a second control terminal coupled to a first current source and to the control terminals of the first and second transistors, the fourth transistor including a first current terminal coupled to the second current terminal of the first transistor, the fourth transistor including a second current terminal coupled to a second current source, and the fourth transistor including a control terminal coupled to a control terminal of the third transistor and to the second current terminal of the fourth transistor; wherein the switching circuit is configured to limit an amount of current drawn by the given one of the plurality of power domains from the power supply during a transition period, the switching circuit further configured to consume zero Direct Current (DC) power outside of the transition period, and wherein the switching circuit further comprises a fifth transistor including a first current terminal coupled to the first current terminal of the fourth transistor, a control terminal coupled to the control terminals of the first and second transistors, and a second current terminal coupled to a third current source, the second current terminal of the fifth transistor configured to provide a signal indicative of whether the transition period has ended.
17. The integrated circuit of claim 16 , further comprising a logic circuit coupled the switching circuitry, the logic circuit configured to reconfigure the switching circuitry in response to a determination that a voltage drop across the switching circuitry is below a threshold value.
18. The integrated circuit of claim 16 , wherein the transition period includes powering up of the given one of the plurality of power domains.