Single port memory that emulates dual port memory
View Patent ↗A single-port memory that operates in single-cycle dual-port mode has a logical capacity of N=k·m memory words and (k+1) single-port RAM having an overall physical capacity of (k+1)·m memory words. A status register holds words identifying which RAM bank has the last data at the i th address in the RAM banks and defining k status words for valid data among the (k+1) RAM banks. Write data is written to the write address of a valid RAM bank for a write operation in the absence of RAM bank read address contention. Write data is written to the write address of a different RAM bank that has no valid data for a write operation if there is contention with the RAM bank read address RADDR of a read operation. The status register is updated to identify the RAM bank of the write operation.
1. A single-port memory capable of operating in single-cycle dual-port mode and having a logical capacity of N=k·m memory words, the memory comprising:
a number (k+1) of single-port random access memory (RAM) banks having an overall physical capacity of (k+1)·m memory words, wherein the RAM banks store write data;
a status register for holding at least N=k·m status words, of which an i th status word identifies which RAM bank has the last data to have been written at an i th address, where iε[0,k·m], wherein k status words are defined for indicating k RAM banks that have valid data among the (k+1) RAM banks;
a write data input and a read data output; and
control logic for receiving read and write enable signals, read and write addresses, and write data from the write data input, for supplying read data from a corresponding read address of a valid RAM bank to the read data output for a read operation, wherein the valid RAM bank for the read operation is determined based on the k status words, for writing the write data from the write data input to a write address of a valid RAM bank for a write operation in the absence of contention with the RAM bank of the read operation, for writing the write data from the write data input to the write address of a next RAM bank that has no valid data for the write operation at the write address in the case of contention with the RAM bank of the read operation, wherein the next RAM bank is determined based on the k status words, wherein the read and write operations are performed in a single cycle, and for updating the status register to identify the RAM bank of the write operation.
2. The memory apparatus of claim 1 , wherein the (k+1) RAM banks each have the same capacity of m words.
3. The memory apparatus of claim 1 , wherein the k·m words of the status register are binary and each word has at least ┌log 2 (k+1)┐ bits, where ┌log 2 (k+1)┐ represents the next integer larger than log 2 (k+1).
4. The memory of claim 1 , wherein the number (k+1) of RAM banks is at least three.
5. The memory of claim 1 , wherein the read and write addresses are random access addresses.
6. A single-port memory that operates in dual-port mode and has a logical capacity of N=2·m words, the memory comprising:
three single-port random access memory (RAM) banks having an overall physical capacity of 3·m memory words;
a status register for holding at least N=2·m status words, of which an i th status word identifies which RAM bank has the last data written at an i th address, where iε[0,2·m], wherein two status words are defined for indicating two RAM banks that have valid data among the three RAM banks;
a write data input and a read data output; and
control logic for receiving read and write enable signals, read and write addresses, and write data from the write data input, for supplying read data from a corresponding read address of a valid RAM bank to the read data output for a read operation, wherein the valid RAM bank for the read operation is determined based on the two status words, for writing the write data from the write data input to a write address of a valid RAM bank for a write operation in the absence of contention with the RAM bank of the read operation, for writing the write data from the write data input to the write address of a next RAM bank that has no valid data for the write operation at the write address in the case of contention with the RAM bank of the read operation, wherein the next RAM bank is determined based on the two status words, wherein the read and write operations are performed in a single cycle, and for updating the status register to identify the RAM bank of the write operation.
7. The memory apparatus of claim 6 , wherein the three RAM banks each have a capacity of m words.
8. The memory apparatus of claim 6 , wherein the 2·m words of the status register are binary and each word has two bits.
9. The memory apparatus of claim 6 , wherein the read and write addresses are random access addresses.
10. A method of operating a single-port memory in a single-cycle dual-port mode, wherein the memory has a logical capacity of N=k·m words and includes a number (k+1) of single-port random access memory (RAM) banks having an overall physical capacity of (k+1)·m memory words, and a status register for holding at least N=k·m status words, the method comprising:
setting data in the status register with an i th status word identifying which RAM bank has the last data written at an i th address, where iε[0,k·m], and defining k status words for indicating k RAM banks that have valid data among the (k+1) RAM banks;
receiving by control logic of the memory, read and write enable signals, read and write addresses, and write data from a write data input;
supplying read data from a corresponding read address of a valid RAM bank to a read data output for a read operation, wherein the valid RAM bank for the read operation is determined based on the k status words;
writing write data from a write data input to a write address of a valid RAM bank for a write operation in the absence of contention with the RAM bank of the read operation;
writing write data from the write data input to the write address of a next RAM bank that has no valid data for the write operation at the write address in the case of contention with the RAM bank of the read operation, wherein the next RAM bank is determined based on the k status words;
wherein the read and write operations are performed in a single cycle; and
updating the status register to identify the RAM bank of the write operation.
11. The method of claim 10 , wherein the (k+1) RAM banks each has a capacity of m words.
12. The method of claim 10 , wherein the k·m words of the status register are binary and each word has at least ┌log 2 (k+1)┐ bits, where ┌log 2 (k+1)┐ represents the next integer larger than log 2 (k+1).
13. The method of claim 10 , wherein the number (k+1) of RAM banks is at least three.
14. The method of claim 10 , wherein the read and write addresses are random access addresses.