System and method for data synchronization across digital device interfaces
View Patent ↗A system for synchronizing and re-ordering data transmitted between first and second clock domains associated with first and second device interfaces, respectively, includes a splitter, an arbiter, a transaction manager, and a read data buffer. The splitter receives a parent read request from one or more data input ports of the first device interface and splits it into one or more read requests. The arbiter receives the one or more read requests and selects one of the read requests and transmits it to the transaction manager. The transaction manager allocates an entry to the read request and then the read request is transmitted to the read data buffer. Thereafter, the read data buffer transmits the read request to the second device interface and transmits received response data to the first device interface.
1. A system for synchronizing and re-ordering data transmitted between first and second clock domains associated with first and second device interfaces, respectively, comprising:
an arbiter connected to one or more data input ports that receives one or more read requests, and selects at least one read request from the one or more read requests based on a predetermined criteria, wherein the one or more data input ports are associated with the first device interface;
a transaction manager, connected to the arbiter, that includes one or more entries organized as one or more linked lists, each linked list corresponding to at least one of the one or more data input ports, wherein the transaction manager allocates a first entry of the one of the entries to the selected read request, wherein the first entry is associated with a first linked list of the one or more linked lists corresponding to the selected read request, determines the first entry associated with a toggle signal, generates a read pointer when the first entry is an initial entry of the first linked list, invalidates the initial entry after generating the read pointer, and designates an entry subsequent to the initial entry as the initial entry;
an asynchronous first-in-first-out (FIFO) module connected to the arbiter and the transaction manager for appending an entry identifier corresponding to the first entry; and
a read data buffer connected to the asynchronous FIFO module and the transaction manager for receiving the selected read request, generating a tag corresponding to the first entry, appending the tag to the selected read request, transmitting the selected read request to the second device interface, receiving a response data from the second device interface, mapping the response data with the corresponding read request entry identifier using the tag associated with the response data and a mapping table that includes a mapping between the one or more entry identifiers and corresponding tags generated by the read data buffer, transmitting the toggle signal corresponding to the first entry, and transmitting the response data corresponding to the first entry to the first device interface.
2. The system of claim 1 , further comprising a splitter connected to the arbiter for receiving a parent read request from the first device interface, and splitting the parent read request into the one or more read requests, wherein a size of the parent read request corresponds to a request transaction size of the first device interface, and a size of each of the one or more read requests corresponds to a request transaction size of the second device interface.
3. The system of claim 1 , wherein the tag corresponds to an addressing scheme associated with the second device interface.
4. The system claim 1 , further comprising a synchronizer connected to the transaction manager and the read data buffer for synchronizing the toggle signal with respect to the first clock domain when the read data buffer transmits the toggle signal to the transaction manager.
5. The system of claim 1 , wherein the read data buffer further includes one or more memory locations, each memory location corresponding to at least one of the one or more entries, and wherein the read data buffer stores the response data in a memory location corresponding to the first entry.
6. The system of claim 5 , wherein the read data buffer further includes one or more multiplexers, each multiplexer including one or more input terminals connected to the one or more memory locations, a select input terminal connected to the transaction manager, and an output terminal connected to the second device interface, wherein the transaction manager selects at least one of the one or more input terminals based on the read pointer transmitted to the select input terminal to enable transmission of the response data from the memory location to the first device interface by way of the output terminal.
7. The system of claim 1 , wherein the first device interface is an advanced extensible interface (AXI) and the second device interface is an eLink interface.
8. The system of claim 1 , wherein the predetermined criteria comprises a round-robin scheduling algorithm.
9. A method for operating a system for synchronizing and re-ordering data transmitted between first and second clock domains, the first and second clock domains being associated with first and second device interfaces, respectively, the system including an arbiter, a transaction manager, an asynchronous first-in-first-out (FIFO) module, and a read data buffer, the transaction manager including one or more entries organized as one or more linked lists, the method comprising:
receiving one or more read requests by the arbiter from one or more data input ports, wherein the one or more data input ports are associated with the first device interface;
selecting at least one read request by the arbiter from the one or more read requests based on one or more criteria;
transmitting the selected read request to the transaction manager by the arbiter;
allocating a first entry of the one or more entries to the selected read request by the transaction manager, wherein each linked list corresponds to at least one data input port of the one or more data input ports, wherein the first entry is associated with a first linked list of the one or more linked lists corresponding to the selected read request;
transmitting the selected read request to the asynchronous FIFO module by the arbiter;
appending an entry identifier corresponding to the first entry to the selected read request by the asynchronous FIFO module;
transmitting the selected read request to the read data buffer;
generating a tag corresponding to the first entry by the read data buffer, wherein the tag corresponds to an addressing scheme associated with the second device interface, wherein the read data buffer stores a mapping table including a mapping between the one or more entry identifiers and corresponding tags generated by the read data buffer;
appending the tag to the selected read request by the read data buffer;
transmitting the selected read request to the second device interface by the read data buffer;
receiving a response data from the second device interface by the read data buffer;
mapping the response data with the corresponding entry identifier using the tag associated with the response data and the mapping table by the read data buffer;
storing the response data in a memory location corresponding to the entry identifier by the read data buffer;
transmitting a toggle signal corresponding to the first entry associated with the response data to the transaction manager for indicating receipt of the response data at the read data buffer;
determining the first entry associated with the toggle signal by the transaction manager;
generating a read pointer by the transaction manager when the first entry is an initial entry in the first linked list;
receiving the read pointer by the read data buffer; and
transmitting the response data corresponding to the first entry to the first device interface by the read data buffer.
10. The method of claim 9 , further comprising receiving a parent read request from the first device interface by a splitter.
11. The method of claim 10 , further comprising splitting the parent read request into the one or more read requests by the splitter, wherein a size of the parent read request corresponds to a transaction size of the first device interface, wherein a size of each of the one or more read requests corresponds to a transaction size of the second device interface.
12. The method of claim 9 , further comprising invalidating the initial entry subsequent to generating the read pointer by the transaction manager.
13. The method of claim 12 , further comprising designating an entry subsequent to the initial entry as the initial entry when the initial entry is invalidated by the transaction manager.
14. The method of claim 9 , further comprising synchronizing the toggle signal with respect to the first clock domain by a synchronizer when the read data buffer transmits the toggle signal to the transaction manager.
15. The method of claim 9 , wherein the one or more criteria area are associated with round-robin scheduling algorithm.