Integrated circuit with degradation monitoring
View Patent ↗An integrated circuit including a degradation monitoring circuit. The degradation monitoring circuit includes a comparison circuit having a programmable delay element including an input coupled to a data node of a timing path and having an output to provide a delayed signal of a data signal of the data node that is delayed by a programmable amount. The comparison circuit includes a logic comparator that provides a logic comparison between a data signal of the data node and the output of the delay element. The monitoring circuit includes a sampling circuit that provides a sampled signal of the output of the logic comparator that is a sampled with respect to a clock signal of the clock signal line. The monitoring circuit includes a hold circuit that provides a signal indicative of a data signal of the data node transitioning within a predetermined time of an edge transition of a clock signal of the clock signal line.
1. An integrated circuit comprising:
a circuit including a timing path, the timing path including an input coupled to a clock signal line, the timing path including a data node;
a degradation monitoring circuit comprising:
a comparison circuit, the comparison circuit comprising:
a programmable delay element including an input coupled to the data node and including an output to provide a delayed signal of a data signal of the data node that is delayed by a programmable amount;
a logic comparator including a first input coupled to the data node and a second input coupled to the output of the programmable delay element, the logic comparator including an output to provide a logic comparison between a data signal of the data node and the output of the delay element;
a sampling circuit including a first input coupled to the output of the logic comparator and a second input coupled to the clock signal line, the sampling circuit including an output to provide a sampled signal of the output of the logic comparator that is a sampled with respect to a clock signal of the clock signal line;
a hold circuit including a first input coupled to the output of the sampling circuit and a second input coupled to the clock signal line, wherein the hold circuit includes an output to provide a signal indicative of a data signal of the data node transitioning within a predetermined time of an edge transition of a clock signal of the clock signal line.
2. The integrated circuit of claim 1 further comprising:
control circuitry including an output to provide a delay signal, wherein the programmable amount is controlled by the delay signal.
3. The integrated circuit of claim 2 further wherein:
the control circuitry receives information of the signal provided by the hold circuit.
4. The integrated circuit of claim 2 wherein the control circuitry is configured to adjust the delay signal to determine a margin error for the circuit.
5. The integrated circuit of claim 4 wherein the control circuitry uses the determined margin error to provide a prediction of remaining useful life of the circuit.
6. The integrated circuit of claim 1 further comprising:
control circuitry, wherein the control circuitry receives information of the signal provided by the hold circuit.
7. The integrated circuit of claim 6 wherein the control circuitry includes storage circuitry configured to store information of the signal provided by hold circuit provided at different times.
8. The integrated circuit of claim 1 wherein the programmable delay element includes a plurality of delay components cascaded in series, wherein each delay component is controlled by a delay signal bit.
9. The integrated circuit of claim 8 wherein each delay component includes delay path and a non delay path, wherein the delay signal bit is used to select which path is to be implemented in providing the programmable amount.
10. A method comprising:
providing a data signal on a data node of a timing path of a circuit;
delaying by a programmable amount, the data signal by a programmable delay element to provide a delayed data signal;
comparing by a logical comparator the data signal to the delayed data signal to provide indications when the data signal and the delayed data signal are at different logic states;
sampling the indications from the logical comparator to provide a sampled signal to indicate indications that occur during a particular portion of a clock cycle of a clock signal provided to the timing path, wherein in response to the sampled signal indicating an indication occurring at a particular portion of the clock cycle, a holding circuit provides an output signal at an indication state, for a particular amount of time, indicating the data signal transitioning within a predetermined time of an edge transition of the clock signal.
11. The method of claim 10 further comprising:
changing the programmable amount to a second programmable amount that is different from the programmable amount;
providing a second data signal on the data node;
delaying by the second programmable amount, the second data signal by the programmable delay element to provide a second delayed data signal;
comparing by a logical comparator the second data signal to the second delayed data signal to provide indications when the second data signal and the second delayed data signal are at different logic states;
sampling the indications from the logical comparator to provide a second sampled signal to indicate indications that occur during a particular portion of a clock cycle of a clock signal provided to the timing path, wherein in response to the second sampled signal indicating an indication occurring at a particular portion of the clock cycle, the holding circuit provides a second output signal at an indication state, for a particular amount of time, indicating the second data signal transitioning within a predetermined time of an edge transition of the clock signal.
12. The method of claim 11 wherein the changing the programmable amount to a second programmable amount is performed in response to the holding circuit providing the output signal at an indication state, for a particular amount of time, indicating the data signal transitioning within a predetermined time of an edge transition of the clock signal.
13. The method of claim 12 wherein changing the programmable amount to a second programmable amount is not performed in response to the output signal indicating that data signal does not transition within the predetermined time of the edge transition of the clock signal.
14. The method of claim 12 wherein the programmable amount is greater than the second programmable amount.
15. The method of claim 11 further comprising:
determining a margin error of the circuit by control circuitry using the output signal and the second output signal.
16. The method of claim 15 , further comprising: using the margin error to determine a remaining useful life of the circuit.
17. The method of claim 15 wherein the control circuitry and the circuit are located on a same integrated circuit.
18. The method of claim 10 further comprising:
performing for a plurality of data signals the steps of providing, delaying, comparing and sampling, wherein the performing the steps includes using a different programmable amount of a plurality of programmable amounts;
determining a largest programmable amount of a plurality of programmable amounts for which the holding circuit does not provide an output signal at an indication state, for a particular amount of time, indicating the data signal of the plurality transitioning within a predetermined time of an edge transition of the clock signal.
19. The method of claim 10 wherein the programmable delay is set by a control circuitry, wherein the control circuitry and the circuit are located on a same integrated circuit.
20. An integrated circuit comprising:
a circuit including a timing path, the timing path including a flip flop, the flip flop including a data input, the flip flop including a clock input coupled to a clock signal line,
a degradation monitoring circuit comprising:
a comparison circuit, the comparison circuit comprising:
a programmable delay element including an input coupled to the data input and including an output to provide a delayed signal of a data signal of the data input that is delayed by a programmable amount;
a logic comparator including a first input coupled to the data input and a second input coupled to the output of the delay element, the logic comparator including an output to provide a logic comparison between a data signal of the data input and the output of the delay element;
a sampling circuit including a first input coupled to the output of the logic comparator and a second input coupled to the clock signal line, the sampling circuit including an output to provide a sampled signal of the output of the logic comparator that is sampled at a portion of a clock cycle of a clock signal of the clock signal line;
a hold circuit including a first input coupled to the output of the sample circuit and a second input coupled to the clock signal line, wherein the hold circuit includes an output to provide a signal indicative of a data signal of the data input transitioning within a predetermined time of an edge transition of a clock signal of the clock signal line.