IP Library Granted Patent US 9,165,023
Granted Patent B2
US 9,165,023 · App. 13/978,251 · Granted Oct 20, 2015

Integrated circuit device and method for determining an index of an extreme value within an array of values

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Quick Facts
Patent No.
US 9,165,023
App. No.
13/978,251
Granted
Oct 20, 2015
Kind
B2
Abstract

An integrated circuit device comprises at least one digital signal processor, DSP, module, the at least one DSP module comprising a plurality of data registers and at least one data execution unit, DEU, module arranged to execute operations on data stored within the data registers. The at least one DEU module is arranged to, in response to receiving an extreme value index instruction, compare a previous extreme value located within a first data register set of the DSP module with at least one input vector data value located within a second data register set of the DSP module, and determine an extreme value thereof. The at least one DEU module is further arranged to, if the determined extreme value comprises an input vector data value located within the second data register set, store the determined extreme value in the first data register set, determine an index value for the determined extreme value, and store the determined index value in the first data register set.

Claims (52)

1. An integrated circuit device comprising:

at least one digital signal processor (DSP) module, the at least one DSP module comprising a plurality of data registers and at least one data execution unit (DEU) module arranged to execute operations on data stored within the data registers;

wherein the at least one DEU module is arranged to, in response to receiving an extreme value index instruction, compare a previous extreme value located within a first data register set of the DSP module with at least one input vector data value located within a second data register set of the DSP module, and determine an extreme value thereof;

wherein the at least one DEU module is further arranged to, if the determined extreme value comprises an input vector data value located within the second data register set, store the determined extreme value in the first data register set, determine an index value for the determined extreme value, and store the determined index value in the first data register set.

2. The integrated circuit device of claim 1 wherein the at least one DEU module is arranged to overwrite the previous extreme value located within the first data register set with the determined extreme value, if the determined extreme value comprises the input vector data value located within the second data register set.

3. The integrated circuit device of claim 1 wherein the at least one DEU module is arranged to overwrite an index value for the previous extreme value located within the first data register set with the determined index value for the determined extreme value, if the determined extreme value comprises the input vector data value located within the second data register set.

4. The integrated circuit device of claim 1 wherein the at least one DEU module is arranged to determine an index value for the determined extreme value based on a current index value located within the first data register set and an index value for a location of the determined extreme value within the second data register set, if the determined extreme value comprises the input vector data value located within the second data register set.

5. The integrated circuit device of claim 4 wherein the at least one DEU module is further arranged to increment the current index value located within the first data register set during execution of the received extreme value index instruction.

6. The integrated circuit device of claim 5 wherein the at least one DEU module is arranged to increment the current index value by an amount equal to an index stride value located within the first data register set during execution of the received extreme value index instruction.

7. The integrated circuit device of claim 1 wherein the first data register set comprises at least one data register arranged to store therein at least one from a group consisting of:

an index stride value;

a previous extreme value;

an index value for the previous extreme value; and

a current index value.

8. The integrated circuit device of claim 1 wherein the extreme value index instruction comprises a maximum value index instruction or a minimum value index instruction.

9. A method for determining an index for an extreme value within an array of values; the method comprising:

comparing a previous extreme value located within a first data register set and at least one input vector data value located within a second data register set and determining an extreme value thereof; and

in response to determining that the extreme value thereof comprises an input vector data value located within the second data register set:

storing the determined extreme value in the first data register set;

determining an index value for the determined extreme value; and

storing the determined index value in the first data register set.

10. The integrated circuit device of claim 2 wherein the at least one DEU module is arranged to overwrite an index value for the previous extreme value located within the first data register set with the determined index value for the determined extreme value, if the determined extreme value comprises the input vector data value located within the second data register set.

11. The integrated circuit device of claim 2 wherein the at least one DEU module is arranged to determine an index value for the determined extreme value based on a current index value located within the first data register set and an index value for a location of the determined extreme value within the second data register set, if the determined extreme value comprises the input vector data value located within the second data register set.

12. The integrated circuit device of claim 3 wherein the at least one DEU module is arranged to determine an index value for the determined extreme value based on a current index value located within the first data register set and an index value for a location of the determined extreme value within the second data register set, if the determined extreme value comprises the input vector data value located within the second data register set.

13. The integrated circuit device of claim 2 wherein the first data register set comprises at least one data register arranged to store therein at least one from a group consisting of:

an index stride value;

a previous extreme value;

an index value for the previous extreme value; and

a current index value.

14. The integrated circuit device of claim 3 wherein the first data register set comprises at least one data register arranged to store therein at least one from a group consisting of:

an index stride value;

a previous extreme value;

an index value for the previous extreme value; and

a current index value.

15. The integrated circuit device of claim 4 wherein the first data register set comprises at least one data register arranged to store therein at least one from a group consisting of:

an index stride value;

a previous extreme value;

an index value for the previous extreme value; and

a current index value.

16. The integrated circuit device of claim 5 wherein the first data register set comprises at least one data register arranged to store therein at least one from a group consisting of:

an index stride value;

a previous extreme value;

an index value for the previous extreme value; and

the current index value.

17. The integrated circuit device of claim 6 wherein the first data register set comprises at least one data register arranged to store therein at least one from a group consisting of:

an index stride value;

a previous extreme value;

an index value for the previous extreme value; and

the current index value.

18. The integrated circuit device of claim 2 wherein the extreme value index instruction comprises a maximum value index instruction or a minimum value index instruction.

19. The integrated circuit device of claim 3 wherein the extreme value index instruction comprises a maximum value index instruction or a minimum value index instruction.

20. The integrated circuit device of claim 4 wherein the extreme value index instruction comprises a maximum value index instruction or a minimum value index instruction.

Assignments (27)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 042985 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051029/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 042762 FRAME 0145. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
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CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051030/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 039361 FRAME 0212. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
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RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050744/0097 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
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CORRECTIVE ASSIGNMENT TO CORRECT THE TO CORRECT THE APPLICATION NO. FROM 13,883,290 TO 13,833,290 PREVIOUSLY RECORDED ON REEL 041703 FRAME 0536. ASSIGNOR(S) HEREBY CONFIRMS THE THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS.. Recorded Feb 20, 2019
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From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
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CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12681366 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded May 9, 2017
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
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CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE PATENTS 8108266 AND 8062324 AND REPLACE THEM WITH 6108266 AND 8060324 PREVIOUSLY RECORDED ON REEL 037518 FRAME 0292. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Feb 1, 2017
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From: FREESCALE SEMICONDUCTOR, INC.
To: NXP USA, INC.
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MERGER Recorded Nov 8, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: NXP USA, INC.
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CORRECTIVE ASSIGNMENT TO CORRECT THE INCORRECT PCT NUMBERS IB2013000664, US2013051970, US201305935 PREVIOUSLY RECORDED AT REEL: 037444 FRAME: 0787. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Oct 17, 2016
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To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
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