Microelectronic packages and methods for the fabrication thereof
View Patent ↗Microelectronic packages and methods for fabricating microelectronic packages are provided. In one embodiment, the method comprises encapsulating a first semiconductor die having one or more core redistribution layers formed thereover in an outer molded body. The outer molded body has a portion, which circumscribes the core redistribution layer. One or more topside redistribution layers are produced over the core redistribution layer. A contact array is formed over the topside redistribution layer and electrically coupled to the first semiconductor die encapsulated in the outer molded body through the topside redistribution layers and the core redistribution layers.
1. A method for fabricating a microelectronic package, comprising:
encapsulating a first semiconductor die having one or more core redistribution layers formed thereover in an outer molded body, the outer molded body having a portion circumscribing the core redistribution layers;
producing one or more topside redistribution layers over the core redistribution layers; and
forming a contact array over the topside redistribution layers and electrically coupled to the first semiconductor die encapsulated in the outer molded body through the topside redistribution layers and the core redistribution layers;
wherein the first semiconductor die is embedded within an inner molded body, wherein encapsulating comprises forming an outer molded body around the inner molded body and the core redistribution lavers, and wherein a second semiconductor die is embedded within the inner molded body and electrically interconnected with the first semiconductor die by the core redistribution layers.
2. The method of claim 1 wherein producing comprises producing one or more topside redistribution layers to extend at least partially over the portion of the outer molded body circumscribing the core redistribution layers.
3. The method of claim 1 wherein encapsulating comprises encapsulating a microelectronic component along with the first semiconductor die, and wherein producing comprises producing the one or more topside redistribution layers to electrically couple the microelectronic component through the one or more core redistribution layers.
4. The method of claim 1 further comprising testing the first semiconductor die and the one or more core redistribution layers prior to encapsulating the first semiconductor die in the outer molded body.
5. The method of claim 1 further comprising:
processing a wafer to produce an array of semiconductor die including the first semiconductor die and the second semiconductor die; and
producing one or more core redistribution layers over the frontside of the wafer prior to singulation thereof.
6. The method of claim 1 wherein encapsulating comprises:
positioning the first semiconductor die, the second semiconductor die, and a plurality of other semiconductor die on a temporary substrate;
dispensing a mold compound over the first semiconductor die, the second semiconductor die, and the plurality of other semiconductor die; and
curing the mold compound to form a molded panel containing the first semiconductor die, the second semiconductor die, and the plurality of other semiconductor die.
7. The method of claim 1 further comprising:
prior to encapsulating the first semiconductor die in the outer molded body, overmolding an array of semiconductor die including the first semiconductor die and the second semiconductor die to produce an initial Redistributed Chip Packaging (RCP) panel;
producing the one or more core redistribution layers over the frontside of the initial RCP panel; and
singulating the initial RCP panel to produce a core package including an inner molded body in which the first semiconductor die and the second semiconductor die are embedded.
8. The method of claim 7 wherein encapsulating comprises overmolding the core redistribution layers and the core package to form the outer molded body surrounding the inner molded body.
9. A method for fabricating a microelectronic package, comprising:
encapsulating a first semiconductor die having one or more core redistribution layers formed thereover in an outer molded body, the outer molded body having a portion circumscribing the core redistribution layers;
producing one or more topside redistribution layers over the core redistribution layers; and
forming a contact array over the topside redistribution layers and electrically coupled to the first semiconductor die encapsulated in the outer molded body through the topside redistribution layers and the core redistribution layers;
wherein encapsulating comprises encapsulating the first semiconductor die and a microelectronic component within the outer molded body, and wherein producing comprises producing one or more topside redistribution layers over the core redistribution layers and electrically interconnecting the first semiconductor die and the microelectronic component.
10. The method of claim 9 wherein the microelectronic component comprises a second semiconductor die over which one or more core redistribution layers have not been formed.
11. The method of claim 9 wherein the microelectronic component comprises a passive microelectronic device, and wherein the topside redistribution layers electrically interconnect the first semiconductor die and the passive microelectronic device to produce a System-in-Package.
12. The method of claim 9 wherein the microelectronic component is encapsulated within the outer molded body at an elevation overlapping with the core redistribution layers.
13. A method for fabricating a microelectronic package, comprising:
forming a Redistributed Chip Packaging (RCP) panel containing a first microelectronic component, one or more core redistribution layers overlying and in ohmic contact with the first microelectronic component, and a second microelectronic component positioned proximate the first microelectronic component and having a portion that is coplanar in elevation with the core redistribution layers;
producing one or more topside redistribution layers over the RCP panel interconnecting the first and second microelectronic component through the core redistribution layers; and
forming a contact array over the topside redistribution layers and electrically coupled to the first and second microelectronic components.
14. The method of claim 13 wherein the first microelectronic component comprises a semiconductor die, and wherein the second microelectronic component comprises a passive microelectronic device.
15. The method of claim 13 further comprising singulating the RCP panel after forming the contact array to yield a plurality of RCP packages, one of which contains the first and second microelectronic components.
16. The method of claim 13 wherein the first microelectronic component comprises a first semiconductor die, and wherein the method further comprises:
processing a semiconductor wafer to produce an array of semiconductor die including the first semiconductor die; and
producing the core redistribution layers over the semiconductor wafer prior to singulation thereof.
17. The method of claim 13 wherein the first microelectronic component comprises a first semiconductor die, and wherein the method further comprises:
overmolding a plurality semiconductor die including the first microelectronic device to produce an initial RCP panel;
producing one or more core redistribution layers over the frontside of the initial RCP panel; and
singulating the initial RCP panel to produce a core RCP package including an inner molded body surrounding the first semiconductor die;
wherein forming comprises forming the RCP panel to contain the core RCP package and microelectronic component.
18. A microelectronic package, comprising:
a first semiconductor die;
one or more core redistribution layers formed over the first semiconductor die;
an outer molded body in which the first semiconductor die is embedded, the outer molded body having a portion extending around the core redistribution layers;
one or more topside redistribution layers formed over the core redistribution layers and the portion of the outer molded body extending around the core redistribution layers;
a microelectronic device embedded in the outer molded body and electrically coupled to the first semiconductor die through the core redistribution layers, through the topside redistribution layers, or a combination thereof; and
a contact array formed over the topside redistribution layers and electrically coupled to the first semiconductor die embedded in the outer molded body through the core redistribution layers and the topside redistribution layers.
19. The microelectronic package of claim 18 wherein the microelectronic device comprises a second semiconductor die electrically coupled to the contact array through the topside redistribution layers.
20. The microelectronic package of claim 18 wherein the microelectronic component is encapsulated within the outer molded body at an elevation overlapping with the core redistribution layers.