Granted Patent B2

US 10,127,998 · App. 14/038,401 · Granted Nov 13, 2018

Abstract

Claims (48)

1. A method of programming a memory, comprising:

selecting one of two different logic states as a selected logic state for programming a first bitcell of the memory, wherein the first bitcell includes a first one-time-programmable (OTP) element and a second OTP element, and a logic state of the first bitcell is based on a difference between resistances of the first and second OTP element after providing a programming current through the first and second OTP elements;

programming a first one-time-programmable (OTP) element of the first bitcell using a first set of conditions to provide a first programming current through the first OTP element intended to achieve a first target resistance in accordance with the selected logic state which results in a first degree of programming of the first OTP element;

programming a second OTP element of the first bitcell using a second set of conditions different from the first set of conditions to provide a second programming current through the second OTP element intended to achieve a second target resistance in accordance with the selected logic state which results in a second degree of programming of the second OTP element, wherein the first and second degrees of programming are visually indistinguishable, wherein the programming the first and second OTP elements occur after the selecting one of two different logic states as the selected logic state; and

determining if the first bitcell has the selected logic state, wherein the determining comprises determining if the first OTP element has a lower resistance than the second OTP element.

2. The method of claim 1 , wherein the determining if the first OTP element has a lower resistance than the second OTP element comprises determining if the first OTP element has a lower resistance than the second OTP element by a margin.

3. The method of claim 1 , wherein:

the first set of conditions and the second set of conditions include programming time;

the programming time is different between the first and second sets of conditions; and

the first set of conditions and the second set of conditions are for causing electromigration.

4. The method of claim 1 wherein the first set of conditions includes a first programming voltage applied to a terminal of the first OTP element and the second set of conditions includes a second programming voltage applied to a terminal of the second OTP element, wherein the first programming voltage supplies a different voltage level than the second programming voltage.

5. A method of programming a memory, comprising:

selecting one of two different logic states as a selected logic state for programming a first bitcell of the memory, wherein the first bitcell includes a first one-time-programmable (OTP) element and a second OTP element, and a logic state of the first bitcell is based on a difference between resistances of the first and second OTP element after providing a programming current through the first and second OTP elements;

programming a first one-time-programmable (OTP) element of the first bitcell using a first set of conditions to provide a first programming current through the first OTP element intended to achieve a first target resistance in accordance with the selected logic state which results in a first degree of programming of the first OTP element;

programming a second OTP element of the first bitcell using a second set of conditions different from the first set of conditions to provide a first second programming current through the second OTP element intended to achieve a second target resistance in accordance with the selected logic state which results in a second degree of programming of the second OTP element, wherein the first and second degrees of programming are visually indistinguishable, wherein the programming the first and second OTP elements occur after the selecting one of two different logic states as the selected logic state;

determining if the first bitcell has the selected logic state;

if the first bitcell does not have the selected logic state:

programming a redundant bitcell to the selected logic state, and

replacing the first bitcell with the redundant bitcell.

6. The method of claim 5 wherein the determining comprises determining if the first OTP element has a lower resistance than the second OTP element.

7. The method of claim 5 , wherein the programming the redundant bitcell comprises:

programming a first OTP element of the redundant bitcell using the first set of conditions which results in a third degree of programming; and

programming a second OTP element of the redundant bitcell using the second set of conditions which results in a fourth degree of programming, wherein the third and fourth degrees of programming are visually indistinguishable.

8. The method of claim 7 , further comprising determining if the redundant bitcell has the selected logic state.

9. The method of claim 8 , wherein the determining if the redundant bitcell has the selected logic state comprises determining if the third OTP element has a lower resistance than the fourth OTP element by a sufficient margin.

10. The method of claim 8 , further comprising: if the redundant bitcell does not have the selected logic state, using error correction coding during reading of the memory.

11. A memory comprising:

a bitcell array comprising a bitcell array of bitcells and a plurality of redundant bitcells, wherein:

each bitcell comprises a first one-time-programmable (OTP) element and a second OTP element and each redundant bitcell comprises a third OTP element and a fourth OTP element;

programming of the first, second, third, and fourth OTP elements causes a visible change with a resulting appearance; and

the resulting appearance from the programming does not indicate a degree of programming if the programming is within a predetermined range of programming conditions; and

programming circuitry coupled to the bitcell array that programs a selected bitcell to a selected state by programming the first OTP element of the selected bitcell with a first programming current using a first set of conditions that are within the predetermined range of programming conditions when the first set of conditions corresponds to the selected state and by programming the second OTP element of the selected bitcell with a second programming current using a second set of conditions that are different from the first set of conditions and are within the predetermined range, wherein the selected state is a particular logic state selected from two different logic states and selected prior to providing the first and second programming currents through the first and second OTP elements,

wherein the programming circuitry determines if the selected bitcell has been programmed to the selected state by determining if a resistance of the first OTP element of the selected bitcell is greater than a resistance of the second OTP element of the selected bitcell.

12. The memory of claim 11 , wherein, if the programming circuitry determines that the selected bitcell has not been programmed to the selected state, the programming circuitry programs a selected redundant bitcell by programming the third OTP element of the selected redundant bitcell using the first set of conditions and the fourth OTP element of the selected redundant bitcell using the second set of conditions.

13. The memory of claim 12 , wherein if the program circuitry determines that the redundant bitcell has the selected state, the program circuitry replaces the selected bitcell with the redundant bitcell.

14. The memory of claim 13 , further comprising:

sensing circuitry, coupled to the memory array, that performs reads of the memory array during a read mode; and

error correction code circuitry coupled to the sensing circuitry that corrects an output that corresponds to the selected bitcell when the selected bitcell and the selected redundant bitcell have not been programmed to the selected state.

15. The memory of claim 11 , wherein the first set of conditions and the second set of conditions includes programming voltage and programming time, and the programming voltage in the first set of conditions supplies a voltage level to a first terminal of the first OTP element that is different from a voltage level supplied by the programming voltage in the second set of conditions to a first terminal of the second OTP element.

16. The memory of claim 11 , wherein the programming by the programming circuitry is by electromigration.

17. A method of programming a memory having a plurality of bitcells, wherein each bitcell comprises a first one-time-programmable (OTP) element and a second OTP element, comprising:

determining a selected bitcell for programming to a selected logic state, wherein the selected logic state is a particular logic state selected from two different logic states, and a logic state of the first bitcell is based on a difference between resistances of the first and second OTP element after providing a programming current through the first and second OTP elements; and

programming the selected bitcell to the selected logic state by applying a first set of conditions to the first OTP element of the selected bitcell to provide a first programming current to the first OTP element to result in a first resistance in the first OTP element and applying a second set of conditions different from the first set of conditions to the second OTP element of the selected bitcell to provide a second programming current to the second OTP element to result in a second resistance in the second OTP element greater than the first resistance, wherein:

the first OTP element changes to a first visible appearance indicative of a resistance in a first range of resistance,

the second OTP element changes to a second visible appearance indicative of a resistance in the first range, and

a comparison of the first visible appearance and the second visible appearance cannot reliably identify which of the first and second OTP elements has the greater resistance; and

determining if the first bitcell has the selected logic state by determining if the first OTP element has a lower resistance than the second OTP element.

18. The method of claim 17 , wherein programming causes electromigration to result in the first resistance, the second resistance, the first visible appearance, and the second visible appearance.

Assignments (18)