Debug method and device for providing indexed trace messages
View Patent ↗A method and information processing system provide trace compression for trace messages. In response to a branch of a conditional branch instruction having not been taken or having been taken, a flag of a history buffer is set or cleared. A trace address message is generated in response to a conditional indirect branch instruction being taken, wherein the trace address message includes address information indicating the destination address of the taken branch, and an index value indicating a corresponding flag of the history buffer. In response to a return from interrupt or return from exception instruction, a predicted return address is compared to an actual return address. A trace address message is generated in response to the predicted and actual return addresses not matching. A trace address message is not generated in response to the predicted and actual return addresses matching.
1. A method comprising:
determining if a branch of a conditional branch instruction has been taken; and
in response to the branch having not been taken, clearing a first flag of an instruction flow history flag buffer (IFFB), otherwise
in response to the branch having been taken, setting the first flag, and generating a trace address message comprising a destination address of the branch and an index identifying a location of the first flag of the IFFB.
2. The method of claim 1 further comprising:
generating a trace history message comprising flags of the IFFB including the first flag.
3. The method of claim 2 , further comprising transmitting the trace history message to an external debugger.
4. The method of claim 2 wherein clearing the first flag includes programming the first flag to a first binary value, and setting the first flag includes programming the first flag to a second binary value that is opposite the first binary value.
5. The method of claim 2 further comprising:
in response to generating the trace history message, clearing the IFFB.
6. The method of claim 2 wherein generating the trace history message is in response to a fullness of the IFFB.
7. The method of claim 6 wherein generating the trace history message is in response to the IFFB being full, wherein the IFFB has a predetermined size.
8. The method of claim 1 wherein generating the trace address message is further in response to the branch being an indirect branch.
9. An information processing system comprising:
a debug module comprising an Instruction Flow history Flag Buffer (IFFB), the debug module configured to determine if a branch of a conditional branch instruction has been taken, to clear a first flag of the IFFB in response to the branch having not been taken, and in response to the branch having been taken the debug module to: set the first flag of the IFFB, and to generate a trace address message identifying a destination address of the branch that includes an index identifying a location of the first flag within the IFFB.
10. The information processing system of claim 9 wherein the debug module is further configured to generate a trace history message comprising the IFFB.
11. The information processing system of claim 10 wherein the debug module is configured to transmit the trace history message to an external debugger.
12. The information processing system of claim 10 wherein the debug module is configured to generate the trace history message in response to a fullness of the IFFB.
13. The information processing system of claim 10 wherein the debug module is configured to generate the trace history message in response to the IFFB being full wherein the IFFB has a predetermined size.
14. The information processing system of claim 10 wherein the debug module is further configured to clear the IFFB in response to generating the trace history message.
15. The information processing system of claim 9 wherein setting and clearing the first flag results in opposite binary bit values.
16. The information processing system of claim 9 wherein the branch is an indirect branch.
17. A method comprising:
receiving, at a debugger, a trace history message from a data processor comprising content of an Instruction flow History flag Buffer (IFFB);
interpreting cleared flags of the IFFB as corresponding to non-taken branch instructions executed at the data processor and set flags of the IFFB as corresponding to taken branch instructions executed a the data processor;
associating first address information from a first trace address message to a first taken branch of a first branch instruction based upon an index of the first trace address message that identifies a first location of a first flag of the IFFB; and
constructing a representation of executed instruction code based on associating the first address information to the first taken branch.
18. The method of claim 17 wherein the first taken branch is an indirect branch.
19. The method of claim 18 wherein an amount of content of the IFFB is a predetermined amount of content.
20. The method of claim 19 further comprising:
associating second address information from a second trace address message to a second taken branch instruction based upon an index of the second trace address message that identifies a second location of a second flag of the IFFB.