SYSTEM AND METHOD FOR ATOMICALLY UPDATING SHARED MEMORY IN MULTIPROCESSOR SYSTEM
A system for operating a shared memory of a multiprocessor system includes a set of processor cores and a corresponding set of core local caches, a set of I/O devices and a corresponding set of I/O device local caches. Read and write operations performed on a core local cache, an I/O device local cache, and the shared memory are governed by a cache coherence protocol (CCP) that ensures that the shared memory is updated atomically.
1 . A method for operating a shared memory of a multiprocessor system, the multiprocessor system including a set of processor cores and a corresponding set of core local caches, and a set of input/output (I/O) devices and a corresponding set of I/O device local caches, the shared memory being shared between the set of processor cores and the set of I/O devices, the set of processor cores including at least one processor core and the set of I/O devices including at least one I/O device, the method comprising:
updating data stored in a core local cache of the set of core local caches by an associated processor core of the set of processor cores;
transmitting the data stored in the core local cache to the shared memory after being updated by the processor core;
flagging data stored in an I/O device local cache of the set of I/O device local caches as invalid by the processor core, subsequent to the transmission of the data stored in the core local cache to the shared memory;
accessing the I/O device local cache by an associated I/O device of the set of I/O devices;
determining a validity of the data stored in the I/O device local cache by the I/O device;
reading the data stored in the I/O device local cache when the data is determined to be valid; and
accessing data stored in the shared memory when the data stored in the I/O device local cache is determined to be invalid, wherein the data stored in the shared memory is accessed by the I/O device.
2 . The method of claim 1 , further comprising locking the core local cache by the processor core when the core local cache is updated by the processor core.
3 . The method of claim 2 , wherein accessing the data stored in the shared memory further comprises:
transmitting the data stored in the shared memory to the I/O device local cache; and
reading the data transmitted from the shared memory to the I/O device local cache, by the I/O device.
4 . The method of claim 3 , wherein the multiprocessor system operates in accordance with a set of cache coherence protocols associated with CoreNet™ coherence fabric.
5 . The method of claim 1 , wherein the set of I/O devices includes at least one of an input/output memory management unit (IOMMU), a pattern matching engine, and a frame classification hardware.
6 . A multiprocessor system, comprising:
a shared memory;
a set of core local caches connected to the shared memory;
a set of input/output (I/O) device local caches, connected to the shared memory, for receiving and storing data stored in the shared memory;
a set of processor cores, connected to the set of core local caches, for updating the data stored in the set of core local caches, wherein at least one processor core is associated with at least one core local cache of the set of core local caches, wherein the at least one processor core locks the at least one core local cache while updating the data stored therein, transmits the data stored in the at least one core local cache to the shared memory, and flags data stored in at least one I/O device local cache of the set of I/O device local caches as invalid, subsequent to the transmission of the data stored in the at least one core local cache to the shared memory; and
a set of I/O devices connected to the set of I/O device local caches, wherein at least one I/O device is associated with the at least one I/O device local cache, wherein the at least one I/O device determines a validity of the data stored in the at least one I/O device local cache, reads the data stored in the at least one I/O device local cache when the data is determined to be valid, and accesses the data stored in the shared memory when the data stored in the at least one I/O device local cache is determined to be invalid.
7 . The multiprocessor system of claim 6 , wherein the shared memory transmits the data stored therein to the least one I/O device local cache after receiving the data stored in the core local cache, wherein the shared memory transmits the data based on a request received from the at least one I/O device.
8 . The multiprocessor system of claim 8 , wherein the at least one I/O device reads the data transmitted by the shared memory to the at least one I/O device local cache.
9 . The multiprocessor system of claim 6 , wherein the set of I/O devices includes at least one of an input/output memory management unit (IOMMU), a pattern matching engine, and a frame classification hardware.
10 . The multiprocessor system of claim 6 , wherein the multiprocessor system operates in accordance with a set of protocols associated with CoreNet™ coherence fabric.